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MCF5274LVM133 数据表(PDF) 7 Page - Motorola, Inc |
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MCF5274LVM133 数据表(HTML) 7 Page - Motorola, Inc |
7 / 76 page Features MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Preliminary Freescale Semiconductor 7 — 16-bit counter — Low power mode support • Phase Locked Loop (PLL) — Reference crystal 8 to 25 MHz — Low power modes supported — Separate CLKOUT and DDR_CLKOUT signals • Four Programmable Interrupt Timers (PITs) • Interrupt Controllers (x2) — Support for 58 independent interrupt sources, organized as follows: – 51 fully-programmable interrupt sources – 7 fixed-level external interrupt sources — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low power modes • DMA Controller — Four fully programmable channels — Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability — Source/destination address pointers that can increment or remain constant — 24-bit transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Two-bus-clock internal access — External request pins for each channel • External Memory Interface — External glueless connections to 8-, 16-, and 32-bit external memory devices (e.g., SRAM, flash, ROM, etc.) — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 16-bit external bidirectional data bus — 24-bit address bus — Eight chip selects — Byte/write enables — Ability to boot from external memories that are 8 or 16 bits wide • DDR SDRAM controller |
类似零件编号 - MCF5274LVM133 |
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类似说明 - MCF5274LVM133 |
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