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AD5392BST-5-REEL 数据表(PDF) 10 Page - Analog Devices |
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AD5392BST-5-REEL 数据表(HTML) 10 Page - Analog Devices |
10 / 44 page AD5390/AD5391/AD5392 Rev. A | Page 10 of 44 TIMING CHARACTERISTICS: SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 6. 3-Wire Serial Interface1 Parameter2, 3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t54 13 ns min 24th SCLK falling edge to SYNC falling edge t6 4 33 ns min Minimum SYNC low time t7 10 ns min Minimum SYNC high time t7A 50 ns min Minimum SYNC high time in readback mode t8 5 ns min Data setup time t9 4.5 ns min Data hold time t10 4 30 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) t12 4 20 ns min 24th SCLK falling edge to LDAC falling edge t13 20 ns min LDAC pulse width low t14 100 ns max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100 ns min LDAC falling edge to DAC output response time t17 8 µs typ DAC output settling time, AD5390/AD5392 t17 6 µs typ DAC output settling time, AD5391 t18 20 ns min CLR pulse width low t19 12 µs max CLR pulse activation time t205 20 ns max SCLK rising edge to SDO valid t214 5 ns min SCLK falling edge to SYNC rising edge t224 8 ns min SYNC rising edge to SCLK rising edge t234 20 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3 See , F , and . Figure 2 igure 3 Figure 4, Figure 5 4 Standalone mode only. 5 Daisy-chain mode only. |
类似零件编号 - AD5392BST-5-REEL |
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类似说明 - AD5392BST-5-REEL |
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