MC100ES8111 datasheet(5/12 Pages) MOTOROLA

部件名	MC100ES8111

功能描述	Low Voltage 1:10 Differential HSTL Clock Fanout Buffer

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制造商	MOTOROLA [Motorola, Inc]

网页	http://www.freescale.com

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Advanced Clock Drivers Device Data

Freescale Semiconductor

5

MC100ES8111

Freescale Confidential Proprietary

NDA Required / Preliminary

Table 6. AC Characteristics (VCC = 3.3 V ± 5%, VCCO = 1.5 V ± 0.1 V or VCCO = 1.8 V ± 0.1 V), TJ = 0°C to +110°C

(1)

1. AC characteristics apply for parallel output termination of 50

Ω to V

TT (GND).

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

REF_SEL= 0, Active Clock Input Pair CLK0, CLK0 (HSTL differential signals)

VDIF

Differential Input Voltage(2) (Peak-to-Peak)

2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.

0.4

V

VX, IN

Differential Cross Point Voltage(3)

3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC)

range and the input swing lies within the VDIF (DC) specification.

0.68

0.9

V

fCLK

Input Frequency

0

625

MHz

tPD

Propagation Delay CLK0 to Qn

VCCO = 1.8 V

VCCO = 1.5 V

700

990

1030

1270

1420

ps

Differential

tSK(PP)

Output-to-Output Skew (Part-to-Part)

VCCO = 1.8 V

VCCO = 1.5 V

570

720

ps

Differential

tSK(P)

Output Pulse Skew(4)

VCCO = 1.8 V

VCCO = 1.5 V

4. Output duty cycle is DC = (0.5 ± 150 ps · fOUT) · 100%. E.g. the DC range at fOUT = 100 MHz is 48.5% < DC < 51.5%.

100

150

ps

REF_SEL = 1, Active Clock Input Pair CLK1, CLK1 (PECL differential signals)

VPP

Differential Input Voltage(5) (Peak-to-Peak)

5. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device

skew.

0.2

1.0

V

VCMR

Differential Input Crosspoint Voltage(6)

6. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR

(AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation

delay, device and part-to-part skew.

1.0

VCC-0.6

V

fCLK

Input Frequency

0

625

MHz

Differential

tPD

Propagation Delay CLK1 to Qn

VCCO = 1.8 V

VCCO = 1.5 V

590

860

910

1220

1360

ps

Differential

tSK(PP)

Output-to-Output Skew (Part-to-Part)

VCCO = 1.8 V

VCCO = 1.5 V

630

770

ps

Differential

tSK(P)

Output Pulse Skew(7)

VCCO = 1.8 V

VCCO = 1.5 V

7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. The output duty cycle is DC = (0.5 ± 200 ps ·

fOUT) · 100%. E.g. the DC range at fOUT = 100 MHz and VCCO = 1.5 V is 48.0% < DC < 52.0%.

150

200

ps

HSTL Clock Outputs (Qn, Qn)

VX, OUT

Output Differential Crosspoint

0.68

0.91

1.1

V

VOH

Output High Voltage

VCCO = 1.8 V

VCCO = 1.5 V

VCCO-0.8 V

VCCO-0.5 V

1.5

V

VOL

Output Low Voltage

0.2

0.8

V

VO(P-P)

Differential Output Voltage (Peak-to-Peak) VCCO = 1.8 V

VCCO = 1.5 V

0.45

0.40

1.0

V

tSK(O)

Output-to-Output Skew

VCCO = 1.8 V

VCCO = 1.5 V

37

60

80

105

ps

Differential

tJIT(CC)

Output Cycle-to-Cycle Jitter RMS (1

σ)

1.0

ps

tr, tf

Output Rise/Fall Time

150

800

ps

20% to 80%

tPDL

(8)

8. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).

Output Disable Time

2.5·T + tPD

3.5·T + tPD

ns

T=CLKn period

tPLE

(9)

9. Propagation delay OE assertion to output enabled (active).

Output Enable Time

3.0·T + tPD

4.0·T + tPD

ns

T=CLKn period

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