ADM1060ARU datasheet(2/45 Pages) AD

部件名	ADM1060ARU

功能描述	Communications System Supervisory/Sequencing Circuit

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ADM1060

–2–

REV. PrJ 11/02

PRELIMINARY TECHNICAL DATA

FEATURES

Faults detected on 7 independent supplies

• 1 High Voltage supply (up to 14.4V)

• 4 Positive Voltage Only Supplies (up to 6V)

• 2 Positive/Negative Voltage supplies (up to +6V OR

down to -6V)

Watchdog Detector Input- Timeout delay programmable

from 200ms to 12.8sec

4 General Purpose Logic Inputs

Programmable Logic Block- combinatorial and sequenc-

ing logic control of all inputs and outputs

9 Programmable Output Drivers

• Open Collector (external resistor required)

• Open Collector with internal pull-up to VDD

• Fast Internal pull-up to VDD

• Open Collector with internal pull-up to VPn

• Fast Internal pull-up to VPn

• Internally charge pumped high drive (for use with

external N- channel FETS- PDO’s 1 to 4 only)

EEPROM- 512 Bytes

Industry Standard 2- Wire Bus Interface (SMBus)

Guaranteed PDO Low with VPn, VH=1V

APPLICATIONS

Central Office Systems

Servers

Infrastructure Network Boards

High density, multi- voltage system cards

GENERAL DESCRIPTION

The ADM1060 is a programmable supervisory/sequencing

device which offers a single chip solution for multiple

power supply fault detection and sequencing in communi-

cations systems.

In central office, servers and other infrastructure systems,

a common backplane dc supply is reduced to multiple

board supplies using dc/dc converters.

These multiple

supplies are used to power different sections of the board

(eg) 3.3V Logic circuits, 5V logic circuits, DSP core and

I/O circuits etc.

There is usually a requirement that cer-

tain sections power up before others (eg) a DSP core to

power up before the DSP I/O or vice versa. This is in

order to avoid damage, miscommunication or latch- up.

The ADM1060 facilitates this, providing supply fault

detection and sequencing/combinatorial logic for up to 7

independent supplies. The 7 Supply Fault Detectors con-

sist of one high voltage detector (up to +14.4V), two bi-

polar voltage detectors (up to +6V OR down to -6V) and

4 positive low voltage detectors (up to +6V).

All of the

detectors can be programmed to detect undervoltage, ov-

ervoltage or out- of window (undervoltage OR overvolt-

age) conditions.

The inputs to these Supply Fault

Detectors are via the VH pin (High Voltage), VBn pins

(positive OR negative) and VPn pins (Positive only) pins

respectively.

Either the VH supply or one of the VPn

supplies is used to power the ADM1060 (whichever is

highest).

This ensures that, in the event of a supply fail-

ure, the ADM1060

is kept alive for as long as possible,

thus enabling a reliable fault flag to be asserted and the

system to be powered down in an ordered fashion.

Other inputs to the ADM1060 include a Watchdog Detec-

tor (WDI) and 4 General Purpose Inputs (GPIn).

The

Watchdog Detector can be used to monitor a processor

clock.

If the clock does not toggle (transition from low to

high or from high to low) within a programmable timeout

period (up to 18 sec.), a fail flag will assert. The 4 Gen-

eral Purpose inputs can be configured as logic buffers or

to detect positive/negative edges and to generate a logic

pulse or level from those edges.

Thus, the user can input

control signals from other parts of their system (eg RE-

SET or POWER_GOOD) to gate the sequencing of the

supplies supervised by the ADM1060.

The ADM1060 features 9 Programmable Driver Outputs

(PDO’s).

All 9 outputs can be configured to be logic

outputs, which can provide multiple functions for the end

user such as RESET generation, POWER_GOOD status,

enabling of LDO’s, Watchdog Timeout assertion etc.

PDO’s 1- 4 have the added feature of being able to pro-

vide an internally charge pumped high voltage for use as

the gate drive of an external N- Channel FET which

could be placed in the path of one of the supplies being

supervised.

All of the inputs and outputs described above are con-

trolled by the Programmable Logic Block Array.

This is

the logic core of the ADM1060.

It is comprised of 9

macrocells, one for each PDO.

These macrocells are

essentially just wide AND gates.

Any/all of the inputs can

be used as an input to these macrocells. The output of a

macrocell can also be used as an input to any macrocell

other than itself (an input to itself would result in a no-

terminating loop).

The PLBA outputs control the PDO’s

of the ADM1060 via delay blocks, where a delay of be-

tween 0 and 500ms can be programmed on the rising and/

or the falling edge of the data. This results in a very flex-

ible sequencing ability.

Thus, for instance, PDO1 can be

programmed so that it will not assert until, say, VP2,

VP3and VP4 supplies are in tolerance, VB1 and VH have

been in tolerance for 200mS, and PDO7 has already been

asserted.

A simple sequencing operation would be to

daisy chain each PLB output into the input of the next

PLB such that PDO9 doesn’t assert until PDO8 asserts,

which in turn doesn’t assert until PDO7 asserts etc.

All of the functional capability described here is program-

mable through the industry standard 2 wire bus (SMBus)

provided.

Device settings can be written to EEPROM

memory for automatic programming of the device on

power-up.

The EEPROM is organised in 512 bytes, half

of which are used to program all of the functions on the

ADM1060.

The other 256 bytes of EEPROM are for

general purpose system use (eg) date codes, system ID etc.

Read/write access to this is also via the 2 wire interface.

In addition, each output state can be directly overdriven

from the serial interface, allowing a further level of con-

trol (eg) a system controlled soft powerdown.

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