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AD652JP-REEL7 数据表(PDF) 9 Page - Analog Devices |
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AD652JP-REEL7 数据表(HTML) 9 Page - Analog Devices |
9 / 29 page AD652 Rev. C | Page 8 of 28 Another way to view this is that the output is a frequency of approximately one-quarter of the clock that has been phase modulated. A constant frequency can be thought of as accumulating phase linearly with time at a rate equal to 2πf radians per second. Therefore, the average output frequency, which is slightly in excess of a quarter of the clock, requires phase accumulation at a certain rate. However, since the SVFC is running at exactly one-quarter of the clock, it does not accumulate enough phase (see Figure 7). When the difference between the required phase (average frequency) and the actual phase equals 2π, a step-in phase is taken where the deficit is made up instantaneously. The output frequency is then a steady carrier that has been phase modulated by a sawtooth signal (see Figure 7). The period of the sawtooth phase modulation is the time required to accumulate a 2π difference in phase between the required average frequency and one quarter of the clock frequency. The sawtooth phase modulation amplitude is 2π. TIME TIME φMOD (t) ACTUAL PHASE EXPECTED PHASE PHASE 2 π 2 π 2 π PHASE MODULATION AVERAGE CARRIER FREQUENCY VOUT (t) = COS (2π× fAVE × t + φMOD (t)) Figure 7. Phase Modulation The result of this synchronism is that the rate at which data may be extracted from the series bit stream produced by the SVFC is limited. The output pulses are typically counted during a fixed gate interval and the result is interpreted as an average frequency. The resolution of such a measurement is determined by the clock frequency and the gate time. For example, if the clock frequency is 4 MHz and the gate time is 4.096 ms, a maximum count of 8,192 is produced by a full-scale frequency of 2 MHz. Thus, the resolution is 13 bits. OVERRANGE Since each reset pulse is only one clock period in length, the full-scale output frequency is equal to one-half the clock frequency. At full scale, the current steering switch spends half of the time on the summing junction; thus, an input current of 0.5 mA can be balanced. In the case of an overrange, the output of the integrator op amp drifts in the negative direction and the output of the comparator remains high. The logic circuits simply settle into a divide-by-two of the clock state. |
类似零件编号 - AD652JP-REEL7 |
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类似说明 - AD652JP-REEL7 |
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