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AD6676 数据表(PDF) 8 Page - Analog Devices

部件名 AD6676
功能描述  Wideband IF Receiver Subsystem
Download  90 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6676 数据表(HTML) 8 Page - Analog Devices

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AD6676
Data Sheet
Rev. D | Page 8 of 90
CLK± TO SYSREF± TIMING DIAGRAM
CLK+
CLK–
SYSREF+
SYSREF–
tSU_SR
tH_SR
Figure 2. SERDES CLK+ to SYSREF+ Timing
DIGITAL CMOS INPUT/OUTPUT SPECIFICATIONS
VDD1 = VDDL = VDDC = VDDQ = VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CMOS INPUT/OUTPUT LEVELS
Input Voltage High
VIH
VDDIO × 0.65
V
Input Voltage Low
VIL
VDDIO × 0.35
V
Output Voltage High
VOH
SDIO/SDO
IOH = 3 mA
VDDIO × 0.7
V
AGCx
IOH = 0.5 mA
VDDIO × 0.7
V
Output Voltage Low
VOL
SDIO/SDO
IOL = 3 mA
0.4
V
AGCx
VOL
IOL = 0.5 mA
0.4
V
Input Capacitance
1
pF
SPI TIMING
See Figure 148, Figure 149, and Figure 150
SCLK Frequency
fSCLK
25
MHz
SCLK Period
tSCLK
40
ns
SCLK Pulse Width High
tHIGH
10
ns
SCLK Pulse Width Low
tLOW
10
ns
SDIO Setup Time
tDS
2
ns
SDIO Hold Time
tDH
2
ns
SPI_RESET Setup Time1
tSPI_RST
Not shown in Figure 148 to Figure 150
2
ms
SCLK Falling Edge to SDO Valid
Propagation Delay
tACCESS
10
ns
CSB Rising Edge to SDIO High-Z
tZ
10
ns
CSB Fall to SCLK Rise Setup Time
tS
2
ns
SCLK Fall to CSB Rise Hold Time
tH
2
ns
1 This is the time required after a software or hardware reset until SPI access is available again.


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