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GS816118D-225I 数据表(PDF) 9 Page - List of Unclassifed Manufacturers |
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GS816118D-225I 数据表(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 40 page Rev: 2.12 9/2002 1/32 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816118/36T-250/225/200/166/150/133 1M x 18, 512K x 36 18Mb Sync Burst SRAMs 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 100-Pin TQFP Commercial Temp Industrial Temp Features • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard package Functional Description Applications The GS816118/36T is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge- triggered Data Output Register. SCD Pipelined Reads The GS816118/36T is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816118/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. -250 -225 -200 -166 -150 -133 Unit Pipeline 3-1-1-1 tKQ tCycle 2.5 4.0 2.7 4.4 3.0 5.0 3.4 6.0 3.8 6.7 4.0 7.5 ns ns 3.3 V Curr (x18) Curr (x36) 280 330 255 300 230 270 200 230 185 215 165 190 mA mA 2.5 V Curr (x18) Curr (x36) 275 320 250 295 230 265 195 225 180 210 165 185 mA mA Flow Through 2-1-1-1 tKQ tCycle 5.5 5.5 6.0 6.0 6.5 6.5 7.0 7.0 7.5 7.5 8.5 8.5 ns ns 3.3 V Curr (x18) Curr (x36) 175 200 165 190 160 180 150 170 145 165 135 150 mA mA 2.5 V Curr (x18) Curr (x36) 175 200 165 190 160 180 150 170 145 165 135 150 mA mA |
类似零件编号 - GS816118D-225I |
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类似说明 - GS816118D-225I |
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