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AT49BV802A 数据表(PDF) 4 Page - ATMEL Corporation |
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AT49BV802A 数据表(HTML) 4 Page - ATMEL Corporation |
4 / 29 page 4 AT49BV802A(T) 3405C–FLASH–9/04 CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t EC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 23 sec- tors (SA0 - SA22) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is t SEC. When the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the oper- ation terminating immediately. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi- cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automati- cally generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified t BP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or program operation was performed successfully. PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a program or erase operation: I/O2, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 10 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49BV802A(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration reg- ister can be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration regis- ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the “Command Definition in Hex” table on page 11, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration regis- ter. The value of the configuration register will affect the operation of the I/O7 status bit as described below. |
类似零件编号 - AT49BV802A |
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类似说明 - AT49BV802A |
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