AD9200ARS datasheet(4/25 Pages) AD

部件名	AD9200ARS

功能描述	CMOS A/D Converter

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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Parameter

Symbol

Min

Typ

Max

Units

Condition

DIGITAL INPUTS

High Input Voltage

VIH

2.4

V

Low Input Voltage

VIL

0.3

V

DIGITAL OUTPUTS

High-Z Leakage

IOZ

–10

+10

µA

Output = GND to VDD

Data Valid Delay

tOD

25

ns

CL = 20 pF

Data Enable Delay

tDEN

25

ns

Data High-Z Delay

tDHZ

13

ns

LOGIC OUTPUT (with DRVDD = 3 V)

High Level Output Voltage (IOH = 50 µA)

VOH

+2.95

V

High Level Output Voltage (IOH = 0.5 mA)

VOH

+2.80

V

Low Level Output Voltage (IOL = 1.6 mA)

VOL

+0.4

V

Low Level Output Voltage (IOL = 50 µA)

VOL

+0.05

V

LOGIC OUTPUT (with DRVDD = 5 V)

High Level Output Voltage (IOH = 50 µA)

VOH

+4.5

V

High Level Output Voltage (IOH = 0.5 mA)

VOH

+2.4

V

Low Level Output Voltage (IOL = 1.6 mA)

VOL

+0.4

V

Low Level Output Voltage (IOL = 50 µA)

VOL

+0.1

V

CLOCKING

Clock Pulsewidth High

tCH

22.5

ns

Clock Pulsewidth Low

tCL

22.5

ns

Pipeline Latency

3

Cycles

CLAMP

2

Clamp Error Voltage

EOC

±20

±40

mV

CLAMPIN = 0.5 V–2.7 V, RIN = 10 Ω

Clamp Pulsewidth

tCPW

2

µsC

IN = 1 µF (Period = 63.5 µs)

NOTES

1See Figures 1a and 1b.

2Available only in AD9200ARS and AD9200KST.

Specifications subject to change without notice.

AD9200

REFTS

REFBS

MODE

AVDD

10k

0.4

VDD

AD9200

REFTS

REFBF

MODE

REFTF

REFBS

4.2k

Figure 1a.

Figure 1b.

AD9200

–3–

REV. E

类似零件编号 - AD9200ARS

制造商	部件名	数据表	功能描述
Analog Devices	AD9200ARS	338Kb / 24P	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter REV. E
	AD9200ARSRL	338Kb / 24P	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter REV. E
	AD9200ARSZ	518Kb / 32P	Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters REV. E

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