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LTC3717 数据表(PDF) 1 Page - Linear Technology |
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LTC3717 数据表(HTML) 1 Page - Linear Technology |
1 / 20 page 1 LTC3717 sn3717 3717fs Wide Operating Range, No RSENSE TM Step-Down Controller for DDR/QDR Memory Termination s VOUT = 1/2 VIN (Supply Splitter) s Adjustable and Symmetrical Sink/Source Current Limit up to 20A s ±0.65% Output Voltage Accuracy s Up to 97% Efficiency s No Sense Resistor Required s Ultrafast Transient Response s True Current Mode Control s 2% to 90% Duty Cycle at 200kHz s tON(MIN) ≤ 100ns s Stable with Ceramic COUT s Dual N-Channel MOSFET Synchronous Drive s Power Good Output Voltage Monitor s Wide VCC Range: 4V to 36V s Adjustable Switching Frequency up to 1.5MHz s Output Overvoltage Protection s Optional Short-Circuit Shutdown Timer s Available in a 16-Pin Narrow SSOP Package s Bus Termination: DDR and QDR Memory, SSTL, HSTL, ... s Notebook Computers, Desktop Servers s Tracking Power Supply The LTC ®3717 is a synchronous step-down switching regulator controller for double data rate (DDR) and Quad Data Rate TM (QDRTM) memory termination. The controller uses a valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Oper- ating frequency is selected by an external resistor and is compensated for variations in VIN. Forced continuous operation reduces noise and RF inter- ference. Output voltage is internally set to half of VREF, which is user programmable. Fault protection is provided by an output overvoltage comparator and optional short-circuit shutdown timer. Soft-start capability for supply sequencing is accom- plished using an external timing capacitor. The regulator current limit level is symmetrical and user programmable. Wide supply range allows operation from 4V to 36V at the VCC input. , LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung. Figure 1. High Efficiency DDR Memory Termination Supply Efficiency vs Load Current + DB CMDSH-3 D1 B320A L1 0.68 µH CVCC 4.7 µF CIN 150 µF 6.3V ×2 VIN 2.5V TO 5.5V VOUT 1.25V ±10A + + COUT 180 µF 4V ×2 M2 Si7840DP 3717 F01a M1 Si7840DP RON 715k CSS 0.1 µF ION VREF TG SW BOOST RUN/SS ITH SGND INTVCC BG PGND VFB PGOOD CB 0.22µF RC 20k LTC3717 CC 470pF 1 µF VCC VCC 5V TO 28V D2 B320A VDD = 2.5V LOAD CURRENT (A) 0 3717 F01b 100 90 80 70 60 50 40 30 20 10 0 2 4 6 8 10 12 14 VIN = 2.5V VIN = 5V VOUT = 1.25V APPLICATIO S FEATURES TYPICAL APPLICATIO DESCRIPTIO |
类似零件编号 - LTC3717 |
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类似说明 - LTC3717 |
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