12-Bit, 105 MSPS/125 MSPS,

IF Sampling ADC

AD9433

Rev. A

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FEATURES

IF sampling up to 350 MHz

2 V p-p analog input range

On-chip clock duty cycle stabilization

On-chip reference and track-and-hold

SFDR optimization circuit

Excellent linearity

DNL: ±0.25 LSB (typical)

INL: ±0.5 LSB (typical)

750 MHz full power analog bandwidth

Power dissipation: 1.35 W (typical) at 125 MSPS

Twos complement or offset binary data format

5.0 V analog supply operation

2.5 V to 3.3 V TTL/CMOS outputs

APPLICATIONS

Cellular infrastructure communication systems

3G single- and multicarrier receivers

IF sampling schemes

Wideband carrier frequency systems

Point-to-point radios

LMDS, wireless broadband

MMDS base station units

Cable reverse path

Communications test equipment

Radar and satellite ground systems

GENERAL INTRODUCTION

The AD9433 is a 12-bit, monolithic sampling analog-to-digital

converter (ADC) with an on-chip track-and-hold circuit and is

designed for ease of use. The product operates up to a 125 MSPS

conversion rate and is optimized for outstanding dynamic per-

formance in wideband and high IF carrier systems.

The ADC requires a 5 V analog power supply and a differential

encode clock for full performance operation. No external refer-

ence or driver components are required for many applications.

The digital outputs are TTL-/CMOS-compatible, and a separate

output power supply pin supports interfacing with 3.3 V or

2.5 V logic.

FUNCTIONAL BLOCK DIAGRAM

12

12

PIPELINE

ADC

T/H

REF

ENCODE

TIMING

OUTPUT

STAGING

AD9433

GND

VREFOUT

VREFIN

D11 TO D0

DFS

SFDR

MODE

ENCODE

ENCODE

AIN

AIN

Figure 1.

A user-selectable, on-chip proprietary circuit optimizes

spurious-free dynamic range (SFDR) vs. signal-to-noise and

distortion (SINAD) ratio performance for different input signal

frequencies, providing as much as 83 dBc SFDR performance

over the dc to 70 MHz band.

The encode clock supports either differential or single-ended

input and is PECL-compatible. The output format is user-

selectable for offset binary or twos complement and provides

an overrange (OR) signal.

Fabricated on an advanced BiCMOS process, the AD9433 is

available in a 52-lead thin quad flat package (TQFP_EP) that

is specified over the industrial temperature range of −40°C to

+85°C. The AD9433 is pin-compatible with the AD9432.

PRODUCT HIGHLIGHTS

1.

IF Sampling.

The AD9433 maintains outstanding ac performance up to

input frequencies of 350 MHz. Suitable for 3G wideband

cellular IF sampling receivers.

2.

Pin-Compatibility with the AD9432.

The AD9433 has the same footprint and pin layout as the

AD9432 12-bit 80 MSPS/105 MSPS ADC.

3.

SFDR Performance.

A user-selectable, on-chip circuit optimizes SFDR

performance as much as 83 dBc from dc to 70 MHz.

4.

Sampling Rate.

At 125 MSPS, the AD9433 is ideally suited for wireless and

wired broadband applications such as LMDS/MMDS and

cable reverse path.