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AD9480 数据表(PDF) 10 Page - Analog Devices

部件名 AD9480
功能描述  8-Bit, 250 MSPS 3.3 V A/D Converter
Download  29 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9480 数据表(HTML) 10 Page - Analog Devices

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AD9480
Rev. A | Page 9 of 28
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in a Logic 1 state to achieve rated
performance; pulse width low is the minimum time that the
clock pulse should be left in a low state. See the timing
implications of changing tEH in the Clocking the AD9480
section. At a given clock rate, these specifications define an
acceptable clock duty cycle.
Crosstalk
Coupling onto one channel being driven by a low level
(−40 dBFS) signal when the adjacent interfering channel
is driven by a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically, and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and taking the peak measurement again.
The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated by the
measured SINAD based on (assuming full-scale input)
6.02
dB
1.76
=
MEASURED
SINAD
ENOB
Full-Scale Input Power
Expressed in dBm. Computed by
=
001
0
10
2
.
log
INPUT
FULLSCALE
FULLSCALE
Z
rms
V
Power
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and
CLK− and the time when all output data bits are within
valid logic levels.
Noise (For Any Range Within the ADC)
This value includes both thermal and quantization noise.
⎟⎟
⎜⎜
×
×
=
10
10
001
dBFS
dBc
dBm
noise
Signal
SNR
FS
Z
V
.
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.


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