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AD9461 数据表(PDF) 6 Page - Analog Devices

部件名 AD9461
功能描述  16-Bit, 130 MSPS IF Sampling ADC
Download  29 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9461 数据表(HTML) 6 Page - Analog Devices

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AD9461
Rev. 0 | Page 5 of 28
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
AD9461BSVZ
Parameter
Temp
Min
Typ
Max
Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Full
2.0
V
Low Level Input Voltage
Full
0.8
V
High Level Input Current
Full
200
μA
Low Level Input Current
Full
−10
+10
μA
Input Capacitance
Full
2
pF
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1
High Level Output Voltage
Full
3.25
V
Low Level Output Voltage
Full
0.2
V
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)
VOD Differential Output Voltage2
Full
247
545
mV
VOS Output Offset Voltage
Full
1.125
1.375
V
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Full
0.2
V
Common-Mode Voltage
Full
1.3
1.5
1.6
V
Input Resistance
Full
1.1
1.4
1.7
Input Capacitance
Full
2
pF
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9461BSVZ
Parameter
Temp
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
130
MSPS
Minimum Conversion Rate
Full
1
MSPS
CLK Period
Full
7.7
ns
CLK Pulse Width High1 (tCLKH)
Full
3.1
ns
CLK Pulse Width Low1 (tCLKL)
Full
3.1
ns
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)
Full
3.35
ns
Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)
Full
2.3
3.6
4.8
ns
Pipeline Delay (Latency)
Full
13
Cycles
Aperture Uncertainty (Jitter, tJ)
Full
60
fsec rms
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.


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