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NTE1853 数据表(PDF) 4 Page - NTE Electronics |
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NTE1853 数据表(HTML) 4 Page - NTE Electronics |
4 / 6 page Timing Characteristics (Cont’d): Parameter Symbol Test Conditions Min Typ Max Unit SDAB (Note 9) Subcode Data Setup Time tSU, tSDAT 40 – – ns Subcode Data Hold Time tHD, tSDAT 0 – – ns Input Rise Time tR – – 20 ns Input Fall Time tF – – 20 ns Outputs WSBD (Note 6 & Note 10) Word Select Setup Time tSU, tWS 40 – – ns Word Select Hold Time tHD, tWS 0 – – ns WSBD (Note 6) Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns DABD (Note 6 & Note 10) Data Setup Time tSU, tDATD 40 – – ns Data Hold Time tHD, tDATD 0 – – ns Outputs (Cont’d) DABD (Note 6) Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns CLBD (Note 6 & Note 10) Clock Period tCK 161 177 197 ns Clock Low Time tCKL 65 – – ns Clock High Time tCKH 65 – – ns Clock Setup Time tSU, tCLD 40 – – ns Clock Hold Time tHD, tCLD 0 – – ns CLBD (Note 6) Output Rise Time tR – – 20 ns Output Fall Time tF – – 20 ns DABD (Note 6 & Note 11) Data Setup Time tSU, tDATBD 40 – – ns Data Hold Time tHD, tDATBD 60 – – ns Note 6. Reference levels = 0.8V and 2.0V Note 7. The signal CLAB can run at either 2.8MHz (1/4 system clock) or 1.4MHz (1/8 system clock) under typical conditions. It does not have a minimum or maximum frequency, but is limited to being 1/4 or 1/8 of the system clock frequency. Note 8. Input setup and hold times measured with respect to clock input from A–chip (CLAB). Refer- ence levels = 0.8V and 2.0V. Note 9. Input setup and hold times measured with respect to subcode burst clock input from A–chip (SCAB). Reference levels = 0.8V and 2.0V. Note10. Output setup and hold times measured with respect to system clock output (XSYS). Note 11. Output setup and hold times measured with respect to clock output (CLBD). |
类似零件编号 - NTE1853 |
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类似说明 - NTE1853 |
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