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CY7C1371C 数据表(PDF) 2 Page - Cypress Semiconductor

部件名 CY7C1371C
功能描述  18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
Download  33 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1371C 数据表(HTML) 2 Page - Cypress Semiconductor

  CY7C1371C Datasheet HTML 1Page - Cypress Semiconductor CY7C1371C Datasheet HTML 2Page - Cypress Semiconductor CY7C1371C Datasheet HTML 3Page - Cypress Semiconductor CY7C1371C Datasheet HTML 4Page - Cypress Semiconductor CY7C1371C Datasheet HTML 5Page - Cypress Semiconductor CY7C1371C Datasheet HTML 6Page - Cypress Semiconductor CY7C1371C Datasheet HTML 7Page - Cypress Semiconductor CY7C1371C Datasheet HTML 8Page - Cypress Semiconductor CY7C1371C Datasheet HTML 9Page - Cypress Semiconductor Next Button
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CY7C1371C
CY7C1373C
Document #: 38-05234 Rev. *D
Page 2 of 33
1
2
3
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPA
DQPB
DQPC
DQPD
MEMORY
ARRAY
E
INPUT
REGISTER
BWC
BWD
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1371C (512K x 36)
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPA
DQPB
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1373C (1M x 18)


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