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AT87C5111-TDSIL 数据表(PDF) 9 Page - ATMEL Corporation |
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AT87C5111-TDSIL 数据表(HTML) 9 Page - ATMEL Corporation |
9 / 86 page 9 AT8xC5111 4190A–8051–11/02 • Exit from IDLE modes will leave the oscillator control bits OSCAEN, OSCBEN and CKS unchanged. Power-down Modes • POWER-DOWN modes are achieved by using any instruction that writes into PCON.1 sfr • Exit from POWER-DOWN mode is achieved either by a hardware Reset, or by an external interruption. • By RST signal: The CPU will restart on OSCA. • By INT0 or INT1 interruptions, if enabled. The oscillators control bits OSCAEN, OSCBEN and CKS will not be changed, so the selected oscillator before entering into Power-down will be activated. Prescaler Divider • An hardware RESET selects the prescaler divider: – CKRL = FFh: internal clock = OscOut/2 (Standard C51 feature) – X2 = 0, • After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide frequency of the selected oscillator: – CKRL = 00h: minimum frequency = OscOut/512 – CKRL = FFh: maximum frequency = OscOut/2 The frequency of the CPU and peripherals clock CkOut is related to the frequency of the main oscillator OscOut by the following formula: F CkOut = FOscOut/(512 - 2*CKRL) Some examples can be found in the table below: • A software instruction which sets X2 bit de-activates the prescaler/divider, so the internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit. Table 1. Power Modes PD IDLE CKS OSCBEN OSCAEN Selected Mode Comment 0 0 1 X 1 NORMAL MODE A OSCA: XTAL clock X X 1 X 0 INVALID No active clock 0 0 0 1 X NORMAL MODE B OSCB: high-speed RC clock XX 0 0 X INVALID 0 1 1 X 1 IDLE MODE A The CPU is off, OSCA supplies the peripherics 0 1 0 1 X IDLE MODE B The CPU is off, OSCB supplies the peripherics 1X X X X TOTAL POWER- DOWN The CPU is off, OSCA and OSCB are stopped F OscOut MHz X2 CKRL F CkOut (Mhz) 12 0 FF 6 12 0 FE 3 12 1 x 12 |
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