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AD7124-8BCPZ 数据表(PDF) 11 Page - Analog Devices |
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AD7124-8BCPZ 数据表(HTML) 11 Page - Analog Devices |
11 / 93 page AD7124-8 Data Sheet Rev. D | Page 10 of 92 Parameter1 Min Typ Max Unit Test Conditions/Comments POWER-DOWN CURRENTS13 Independent of power mode Standby Current IAVDD 7 15 µA LDOs on only IIOVDD 8 20 µA Power-Down Current IAVDD 1 3 µA IIOVDD 1 2 µA 1 Temperature range = −40°C to +125°C. 2 These specifications are not production tested but are supported by characterization data at the initial product release. 3 FS is the decimal equivalent of the FS[10:0] bits in the filter registers. 4 The nonlinearity is production tested in full power mode. For the other power modes, this specification is supported by characterization data at the initial product release. 5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 6 Recalibration at any temperature removes these errors. 7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C. 8 When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain). 9 Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain). 10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and 60 Hz rejection. 11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1. 12 When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode. 13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled. TIMING CHARACTERISTICS AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, unless otherwise noted. Table 3. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments t3 100 ns SCLK high pulse width t4 100 ns SCLK low pulse width t12 Delay between consecutive read/write operations 3/MCLK3 ns Full power mode 12/MCLK ns Mid power mode 24/MCLK ns Low power mode t13 µs DOUT/RDY high time if DOUT/RDY is low and the next conversion is available 6 µs Full power mode 25 µs Mid power mode 50 µs Low power mode t14 SYNC low pulse width 3/MCLK ns Full power mode 12/MCLK ns Mid power mode 24/MCLK ns Low power mode READ OPERATION t1 0 80 ns CS falling edge to DOUT/RDY active time t24 0 80 ns SCLK active edge5 to data valid delay t56, 7 10 80 ns Bus relinquish time after CS inactive edge t6 0 ns SCLK inactive edge to CS inactive edge t78 SCLK inactive edge to DOUT/RDY high 10 ns The DOUT_RDY_DEL bit is cleared, the CS_EN bit is cleared 110 ns The DOUT_RDY_DEL bit is set, the CS_EN bit is cleared t7A7 t5 ns Data valid after CS inactive edge, the CS_EN bit is set |
类似零件编号 - AD7124-8BCPZ |
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类似说明 - AD7124-8BCPZ |
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