数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

AD7124-8BCPZ 数据表(PDF) 11 Page - Analog Devices

部件名 AD7124-8BCPZ
功能描述  8-Channel, Low Noise, Low Power, 24-Bit Sigma-Delta ADC with PGA and Reference
Download  93 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7124-8BCPZ 数据表(HTML) 11 Page - Analog Devices

Back Button AD7124-8BCPZ Datasheet HTML 7Page - Analog Devices AD7124-8BCPZ Datasheet HTML 8Page - Analog Devices AD7124-8BCPZ Datasheet HTML 9Page - Analog Devices AD7124-8BCPZ Datasheet HTML 10Page - Analog Devices AD7124-8BCPZ Datasheet HTML 11Page - Analog Devices AD7124-8BCPZ Datasheet HTML 12Page - Analog Devices AD7124-8BCPZ Datasheet HTML 13Page - Analog Devices AD7124-8BCPZ Datasheet HTML 14Page - Analog Devices AD7124-8BCPZ Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 93 page
background image
AD7124-8
Data Sheet
Rev. D | Page 10 of 92
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
POWER-DOWN CURRENTS13
Independent of power mode
Standby Current
IAVDD
7
15
µA
LDOs on only
IIOVDD
8
20
µA
Power-Down Current
IAVDD
1
3
µA
IIOVDD
1
2
µA
1
Temperature range = −40°C to +125°C.
2
These specifications are not production tested but are supported by characterization data at the initial product release.
3
FS is the decimal equivalent of the FS[10:0] bits in the filter registers.
4
The nonlinearity is production tested in full power mode. For the other power modes, this specification is supported by characterization data at the initial product
release.
5
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
6
Recalibration at any temperature removes these errors.
7
Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C.
8
When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
9
Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
10
REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and
60 Hz rejection.
11
When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.
12
When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode.
13
The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.
TIMING CHARACTERISTICS
AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, Input
Logic 0 = 0 V, Input Logic 1 = IOVDD, unless otherwise noted.
Table 3.
Parameter1, 2
Min
Typ
Max
Unit
Test Conditions/Comments
t3
100
ns
SCLK high pulse width
t4
100
ns
SCLK low pulse width
t12
Delay between consecutive read/write operations
3/MCLK3
ns
Full power mode
12/MCLK
ns
Mid power mode
24/MCLK
ns
Low power mode
t13
µs
DOUT/RDY high time if DOUT/RDY is low and the next
conversion is available
6
µs
Full power mode
25
µs
Mid power mode
50
µs
Low power mode
t14
SYNC low pulse width
3/MCLK
ns
Full power mode
12/MCLK
ns
Mid power mode
24/MCLK
ns
Low power mode
READ OPERATION
t1
0
80
ns
CS falling edge to DOUT/RDY active time
t24
0
80
ns
SCLK active edge5 to data valid delay
t56, 7
10
80
ns
Bus relinquish time after CS inactive edge
t6
0
ns
SCLK inactive edge to CS inactive edge
t78
SCLK inactive edge to DOUT/RDY high
10
ns
The DOUT_RDY_DEL bit is cleared, the CS_EN bit is
cleared
110
ns
The DOUT_RDY_DEL bit is set, the CS_EN bit is cleared
t7A7
t5
ns
Data valid after CS inactive edge, the CS_EN bit is set


类似零件编号 - AD7124-8BCPZ

制造商部件名数据表功能描述
logo
Analog Devices
AD7124-8BCPZ AD-AD7124-8BCPZ Datasheet
1Mb / 91P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
AD7124-8BCPZ-RL AD-AD7124-8BCPZ-RL Datasheet
1Mb / 91P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
AD7124-8BCPZ-RL7 AD-AD7124-8BCPZ-RL7 Datasheet
1Mb / 91P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
More results

类似说明 - AD7124-8BCPZ

制造商部件名数据表功能描述
logo
Analog Devices
AD7124-8 AD-AD7124-8 Datasheet
1Mb / 91P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
ADFS7124-8 AD-ADFS7124-8 Datasheet
2Mb / 93P
   8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
Rev. 0
AD7124-4 AD-AD7124-4 Datasheet
1Mb / 90P
   4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
AD7124-4-EP AD-AD7124-4-EP Datasheet
272Kb / 17P
   4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
Rev. 0
ADFS7124-4 AD-ADFS7124-4 Datasheet
3Mb / 93P
   4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
Rev. 0
AD7193 AD-AD7193_17 Datasheet
1Mb / 57P
   24-Bit Sigma-Delta ADC with PGA
AD7190 AD-AD7190 Datasheet
178Kb / 21P
   4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
Rev.PrD 7/08
AD7194 AD-AD7194_17 Datasheet
1Mb / 55P
   24-Bit Sigma-Delta ADC with PGA
logo
Maxim Integrated Produc...
MAX11410A MAXIM-MAX11410A Datasheet
1Mb / 95P
   24-Bit, Multichannel, Low-Power 1.9ksps Delta-Sigma ADC with PGA
Rev 0; 10/20
logo
Intersil Corporation
ISL26102AVZ INTERSIL-ISL26102AVZ Datasheet
909Kb / 21P
   Low-Noise 24-bit Delta Sigma ADC
October 12, 2012
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com