LTC3831 datasheet(13/20 Pages) LINER

部件名	LTC3831

功能描述	High Power Synchronous Switching Regulator Controller for DDR Memory Termination

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制造商	LINER [Linear Technology]

网页	http://www.linear.com

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LTC3831

3831f

APPLICATIO S I FOR ATIO

Power MOSFETs

Two N-channel power MOSFETs are required for most

LTC3831 circuits. These should be selected based prima-

rily on threshold voltage and on-resistance considerations.

Thermal dissipation is often a secondary concern in high

efficiency designs. The required MOSFET threshold should

be determined based on the available power supply volt-

ages and/or the complexity of the gate drive charge pump

scheme. In 3.3V input designs where an auxiliary 12V

supply is available to power PVCC1 and PVCC2, standard

MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be

used with good results. The current drawn from this sup-

ply varies with the MOSFETs used and the LTC3831’s

operating frequency, but is generally less than 50mA.

LTC3831 applications that use 5V or lower VIN voltage and

doubling/tripling charge pumps to generate PVCC1 and

PVCC2, do not provide enough gate drive voltage to fully

enhance standard power MOSFETs. Under this condition,

the effective MOSFET RDS(ON) may be quite high, raising

the dissipation in the FETs and reducing efficiency. Logic-

level FETs are the recommended choice for 5V or lower

voltage systems. Logic-level FETs can be fully enhanced

with a doubler/tripling charge pump and will operate at

maximum efficiency.

After the MOSFET threshold voltage is selected, choose

the RDS(ON) based on the input voltage, the output voltage,

allowable power dissipation and maximum output cur-

rent. In a typical LTC3831 circuit operating in continuous

mode, the average inductor current is equal to the output

load current. This current flows through either Q1 or Q2

with the power dissipation split up according to the duty

cycle:

DC Q

V

DC Q

V

VV

V

OUT

IN

OUT

IN

OUT

IN

()

–

1

21

=

==

The RDS(ON) required for a given conduction loss can now

be calculated by rearranging the relation P = I2R.

R

P

DC Q

I

VP

VI

R

P

DC Q

I

VP

VV

I

DS ON Q

MAX Q

LOAD

IN

MAX Q

OUT

LOAD

DS ON Q

MAX Q

LOAD

IN

MAX Q

IN

OUT

LOAD

()

() • (

)

•

•(

)

() • (

)

•

(–

) • (

)

1

2

1

2

1

2

==

PMAX should be calculated based primarily on required

efficiency or allowable thermal dissipation. A typical high

Figure 8. Typical Application with VTT = 0.6 • VDDQ

TG

IMAX

IFB

BG

PGND

GND

R+

FB

VCC

SS

FREQSET

SHDN

COMP

PVCC2

MBR0530T1

5V

10k

1k

0.1

µF

0.1

µF

LO

1.2

µH

Q2

CIN: SANYO POSCAP 6TPB330M

COUT: SANYO POSCAP 4TPB470M

Q1, Q2: SILICONIX Si4410DY

COUT

470

µF

×3

VTT

1.5V

±6A

2k

1%

10k

1%

3831 F08

Q1

MBRS340T3

VDDQ

2.5V

LTC3831

1

µF

SHDN

+

4.7

µF

PVCC1

R–

+

CIN

330

µF

×2

+

0.1

µF

C1

33pF

0.01

µF

130k

CC

1500pF

RC

15k

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