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LM98503CCVV 数据表(PDF) 14 Page - National Semiconductor (TI) |
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LM98503CCVV 数据表(HTML) 14 Page - National Semiconductor (TI) |
14 / 25 page www.national.com 14 System Overview 1.0 Introduction The LM98503 is a 10-bit, complete analog-to-digital camera signal processor for use with CCD imager systems operating from a single +3 Volt supply. The internal processing is carefully optimized to maintain the signal-to-noise ratio and excellent dynamic performance of most popular CCD imagers. The system block diagram of the LM98503, shown on the cover page of the datasheet, highlights the main features of the device: correlated double sampling (CDS), 0-32dB digitally programmable gain amplifier (PGA), digital black level correction feedback loop, 8-bit DAC, analog clamp, bandgap voltage reference, and a 10-bit, 18MHz analog-to-digital converter. 1.1 Correlated Double Sampling Correlated double sampling (CDS) is a key feature in CCD image processors. The sampling process consists of two samples being taken for each pixel. The first stores the reset voltage of the input pixel, and the second sample stores the video signal amplitude. The two samples are subtracted from one another, effectively removing the reset error offset of each pixel. This sampling system operates from 1 to 18MHz. . Figure 9: Correlated Double Sampling 1.2 Programmable Gain Amplifier The amplifier has a gain ranging from 0-32dB, and is “linear in dB” as shown in Figure 15. The PGA is addressed via an 8 bit word downloaded through the serial interface. 1.3 Black Level Clamp CCD signal processors require a reference level for the proper handling of input signals; this reference level is commonly referred to as the black level. The LM98503 is designed to determine a signal’s black level during the CCD imager’s optical black pixels. The LM98503 provides both an analog clamp and a digital black level correction loop. Pulsing the ACLP pin during optical black pixels causes the analog clamp circuitry to remove the offset associated with the input signal. Pulsing the BLKCLP pin during dummy black pixels at the begining of a horizontal line enables the digital black level correction loop. Black level correction may be performed through one of two available methods- automatic or manual. In automatic mode, the black level is sampled from the ADC output during black pixels by setting the BLKCLP input of the LM98503. The ADC black level output value is then averaged over eight pixels and subtracted from the desired black level code stored in the black level configuration register. The result of the subtraction may then be integrated by a preset scaling factor, effectively smoothing any sharp transitions present in the black level signal, before the resulting error is finally applied to the input of the PGA as an analog offset generated by the DAC. The offset integration scaling factor is stored in two bits of the software control register 0, and the values available range from full offset to offset divided-by-16. In addition, an offset output enable bit is provided in the software control register 0, which when set, routes the offset value to the digital output bus rather than the DAC. Use of the automatic mode involves enabling the black level offset auto-calibration bit in the software control register 0 through the serial interface. Refer to Figure 10. Figure 10: Digital Black Level Correction Loop The manual method is intended for use with processing systems where the desired black level correction loop is external to the LM98503. In this mode, up to four available configuration registers may be used to store predetermined offset values that will be applied on a pixel-rate basis. During the vertical interval, new values may be stored in these registers for each horizontal line. 1.4 Auxiliary Input The LM98503 includes a high-level video switch that allows a an auxiliary video signal to be selected instead of the camera image. When the auxiliary input is selected, the PGA gain and DAC offset are fixed to the value in register 0, so the appropriate gain and offset values should be written to PGA gain and DAC offset register 0 prior to AUX IN usage. 1.5 Analog Clamp During optical black pixels, a signal appears at the CCD output. This signal is generally refered to as the “black signal level”. This signal may be seen by the CDS circuitry as a valid video signal rather than the actual black level signal; therefore, the LM98503 provides an analog clamp designed to eliminate this black signal level. Pulsing the analog input pin, ACLP, causes the output of the CDS to be sampled by the analog clamp circuitry. Subsequently, an adjustment is made to the CDS reference voltages by the analog clamp to effectively eliminate any signal level present during black pixels. 10-Bit Analog-to-Digital Converter The selected imager’s analog signal is sampled by the CDS and amplified to match the input requirements of the 10-bit analog to digital converter by the PGA. The final step performed by the system is to convert the selected analog image to digital values with a 10 bits of resolution. The ADC has differential inputs which aids in the coping with headroom constraints common to +3 Volt systems. Data is acquired at the falling edge of the clock and is available at the digital output pins 7.0 clock cycles plus tOD later.Internal Timing Generation All if the necessary clocks for the CDS and ADC operation are generated internally from the LM98503’s master clock input. The CDS sampling clocks may be overridden by the user via the SHP and SHD clock inputs. As depicted in Figure 4 and Figure 5, there are two signals generated internally for CDS sampling CCD nn+1 n+2 Reset Voltage Video Signal Black Pixels CDS + PGA ADC Output Data Pixel Averaging BLKCLP - Black Level Register Offset Integration DAC 10 Analog Offset Register Automatic Calibration Offset |
类似零件编号 - LM98503CCVV |
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类似说明 - LM98503CCVV |
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