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K4H1G0438M Datasheet(数据表) 3 Page - Samsung semiconductor

部件型号  K4H1G0438M
说明  1Gb M-die DDR SDRAM Specification
下载  23 Pages
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
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K4H1G0438M Datasheet(HTML) 3 Page - Samsung semiconductor

 
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DDR SDRAM
DDR SDRAM 1Gb M-die (x4, x8)
Revision 1.0 October, 2004
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
*CL : CAS Latency
Operating Frequencies
B3(DDR333@CL=2.5)
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
Speed @CL2
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
133MHz
133MHz
Ordering Information
Part No.
Org.
Max Freq.
Interface
Package
K4H1G0438M-TC/LB3
256M x 4
B3(DDR333@CL=2.5)
SSTL2
66pin TSOP II
K4H1G0438M-TC/LA2
A2(DDR266@CL=2)
K4H1G0438M-TC/LB0
B0(DDR266@CL=2.5)
K4H1G0838M-TC/LB3
128M x 8
B3(DDR333@CL=2.5)
K4H1G0838M-TC/LA2
A2(DDR266@CL=2)
K4H1G0838M-TC/LB0
B0(DDR266@CL=2.5)
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