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GS8182D09BGD-333 数据表(PDF) 9 Page - GSI Technology |
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GS8182D09BGD-333 数据表(HTML) 9 Page - GSI Technology |
9 / 36 page GS8182D08/09/18/36BD-400/375/333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03d 11/2011 9/36 © 2007, GSI Technology Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations. Power-Up Sequence 1. Power-up and maintain Doff at low state. 1a. Apply VDD. 1b. Apply VDDQ. 1c. Apply VREF (may also be applied at the same time as VDDQ). 2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high. 3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled. Note: If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 ns to reset the DLL after the clocks become stablized. DLL Constraints • The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar.) • The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock frequency. • If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage. Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock. |
类似零件编号 - GS8182D09BGD-333 |
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类似说明 - GS8182D09BGD-333 |
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