Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table

A

W

BWn/NWn BWn/NWn

Input Next State

D

D

K



K



K



K



K

K 

K



K



V

0

0

0

Write Byte Dx0, Write Byte Dx1

D0

D1

V

0

0

1

Write Byte Dx0, Write Abort Byte Dx1

D0

X

V

0

1

0

Write Abort Byte Dx0, Write Byte Dx1

X

D1

X

0

1

1

Write Abort Byte Dx0, Write Abort Byte Dx1

X

X

X

1

X

X

Deselect

X

X

Notes:

1. X = Don’t Care, H = High, L = Low, V = Valid.

2. W is evaluated on the rising edge of K.

3. D0 and D1 are the first and second data input transfers in a write.

4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.). NWn represents any of the Nybble Write Enable inputs (NW0,

NW1).

GS8662Q07/10/19/37BD-357/333/300/250/200

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02c 8/2017

9/28

© 2011, GSI Technology

x36 Byte Write Enable (BWn) Truth Table

BW0

BW1

BW2

BW3

D0–D8

D9–D17

D18–D26

D27–D35

1

1

1

1

Don’t Care

Don’t Care

Don’t Care

Don’t Care

0

1

1

1

Data In

Don’t Care

Don’t Care

Don’t Care

1

0

1

1

Don’t Care

Data In

Don’t Care

Don’t Care

0

0

1

1

Data In

Data In

Don’t Care

Don’t Care

1

1

0

1

Don’t Care

Don’t Care

Data In

Don’t Care

0

1

0

1

Data In

Don’t Care

Data In

Don’t Care

1

0

0

1

Don’t Care

Data In

Data In

Don’t Care

0

0

0

1

Data In

Data In

Data In

Don’t Care

1

1

1

0

Don’t Care

Don’t Care

Don’t Care

Data In

0

1

1

0

Data In

Don’t Care

Don’t Care

Data In

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

0

0

1

0

Data In

Data In

Don’t Care

Data In

1

1

0

0

Don’t Care

Don’t Care

Data In

Data In

0

1

0

0

Data In

Don’t Care

Data In

Data In

1

0

0

0

Don’t Care

Data In

Data In

Data In

0

0

0

0

Data In

Data In

Data In

Data In