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AD7921AUJ-R2 数据表(PDF) 8 Page - Analog Devices |
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AD7921AUJ-R2 数据表(HTML) 8 Page - Analog Devices |
8 / 28 page AD7911/AD7921 Rev. 0 | Page 8 of 28 TIMING EXAMPLES Figure 6 and Figure 7 show some of the timing parameters from the Timing Specifications section. Timing Example 1 As shown in Figure 7, when fSCLK = 5 MHz and the throughput is 250 kSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 4 µs With t2 = 10 ns minimum, then tACQ is 1.49 µs, which satisfies the requirement of 290 ns for tACQ. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 960 ns for tQUIET, satisfying the minimum requirement of 30 ns. Timing Example 2 The AD7921 can also operate with slower clock frequencies. As shown in Figure 7, when fSCLK = 2 MHz and the throughput rate is 100 KSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 10 µs With t2 = 10 ns minimum, then tACQ is 3.74 µs, which satisfies the requirement of 290 ns for tACQ. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 2.46 µs for tQUIET, satisfying the minimum requirement of 30 ns. In this example, as with other slower clock values, the signal might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7. ZERO X 12 34 5 13 14 15 16 X CHN X X X X X X CHN X DB11 DB10 DB2 DB1 DB0 Z t2 t6 t4 t8 t9 t3 t7 t5 t10 t1 tQUIET tCONVERT SCLK CS DOUT THREE-STATE THREE-STATE DIN B Figure 6. AD7921 Serial Interface Timing Diagram 12 3 4 5 13 14 15 16 tQUIET tACQUISITION 1/THROUGHPUT 12.5(1/fSCLK) tCONVERT BC SCLK CS t10 t2 Figure 7. Serial Interface Timing Example |
类似零件编号 - AD7921AUJ-R2 |
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类似说明 - AD7921AUJ-R2 |
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