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74LVX74M 数据表(PDF) 4 Page - Fairchild Semiconductor

部件名 74LVX74M
功能描述  Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

74LVX74M 数据表(HTML) 4 Page - Fairchild Semiconductor

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4
AC Electrical Characteristics
Note 5: Parameter guaranteed by design. tOSLH
|tPLHm–tPLHn|, tOSLH
|tPHLm–tPHLn|
Capacitance
Note 6: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Symbol
Parameter
VCC
TA 25qCTA 40qC to 85qC
Units
CL (pF)
(V)
Min
TypMax
MinMax
tPLH
Propagation Delay
2.7
7.3
15
1.0
18.5
ns
15
tPHL
CPn to Qn or Qn
9.8
18.5
1.0
22
50
3.3
r 0.3
5.7
9.7
1.0
11.5
15
8.2
13.2
1.0
15
50
tPLH
Propagation Delay
2.7
8.4
15.6
1.0
18.5
ns
15
tPHL
CDn to SDn to Qn or Qn
10.9
19.1
1.0
22
50
3.3
r 0.3
6.6
10.1
1.0
12
15
9.1
13.6
1.0
15.5
50
tW
CPn or CDn or SDn
2.7
8.5
10
ns
Pulse Width
3.3
r 0.3
6
7
tS
Setup Time
2.7
8.0
9.5
ns
Dn to CPn
3.3
r 0.3
5.5
6.5
tH
Hold Time
2.7
0.5
0.5
ns
Dn to CPn
3.3
r 0.3
0.5
0.5
tREC
Recovery Time
2.7
6.5
7.5
ns
CPn or SDn to CPn
3.3
r 0.3
5.0
5.0
fMAX
Maximum Clock Frequency
2.7
55
135
50
MHz
15
45
60
40
50
3.3
r 0.3
95
145
80
15
60
85
50
50
tOSLH
Output to Output Skew
2.7
1.5
1.5
ns
50
tOSHL
(Note 5)
3.3
1.5
1.5
Symbol
Parameter
TA 25qCTA 40qC to 85qC
Units
Min
Typ
Max
Min
Max
CIN
Input Capacitance
4
10
10
pF
CPD
Power Dissipation
25
pF
Capacitance (Note 6)


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