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HCPL-0930 数据表(PDF) 9 Page - Agilent(Hewlett-Packard) |
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HCPL-0930 数据表(HTML) 9 Page - Agilent(Hewlett-Packard) |
9 / 12 page 9 Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at T A=+25°C, VDD1 = VDD2 = +5.0 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Quiescent Supply Current 1 IDD1 mA VIN = 0V HCPL-9000/-0900 0.012 0.018 HCPL-9030/-0930 0.012 0.018 HCPL-9031/-0931 2.5 3.0 HCPL-900J/-090J 0.024 0.036 HCPL-901J/-091J 5.0 6.0 HCPL-902J/-092J 2.5 3.0 Quiescent Supply Current 2 I DD2 mA V IN = 0V HCPL-9000/-0900 5.0 6.0 HCPL-9030/-0930 5.0 6.0 HCPL-9031/-0931 2.5 3.0 HCPL-900J/-090J 8.0 12.0 HCPL-901J/-091J 5.0 6.0 HCPL-902J/-092J 6.0 9.0 Logic Input Current IIN -10 10 µA Logic High Output Voltage V OH V DD2 – 0.1 V DD2 VI OUT = -20 µA, VIN =VIH 0.8*VDD2 V DD2 – 0.5 V I OUT = -4 mA, VIN =VIH Logic Low Output Voltage VOL 0 0.1 V IOUT= 20 µA, VIN=VIL 0.5 0.8 V IOUT= 4 mA, VIN=VIL Switching Specifications Maximum Data Rate 100 110 MBd C L = 15 pF Clock Frequency fmax 50 MHz Propagation Delay Time to Logic tPHL 10 15 ns Low Output Propagation Delay Time to Logic tPLH 10 15 ns High Output Pulse Width tPW 10 ns Pulse Width Distortion[1] |PWD| 2 3 ns |t PHL – tPLH| Propagation Delay Skew[2] tPSK 46 ns Output Rise Time (10 – 90%) tR 13 ns Output Fall Time (10 – 90%) tF 13 ns Propagation Delay Enable to Output (Single Channel) High to High Impedance tPHZ 35 ns Low to High Impedance t PLZ 35 ns High Impedance to High t PZH 35 ns High Impedance to Low tPZL 35 ns Channel-to-Channel Skew tCSK 23 ns (Dual and Quad Channels) Common Mode Transient Immunity |CMH| 15 18 kV/ µsV cm = 1000V (Output Logic High or Logic Low) [3] |CM L| Notes: 1. PWD is defined as |t PHL -tPLH|. %PWD is equal to the PWD divided by the pulse width. 2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C. 3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining V OUT < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. |
类似零件编号 - HCPL-0930 |
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类似说明 - HCPL-0930 |
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