数据搜索系统,热门电子元器件搜索 |
|
HCPL-0900 数据表(PDF) 10 Page - Agilent(Hewlett-Packard) |
|
HCPL-0900 数据表(HTML) 10 Page - Agilent(Hewlett-Packard) |
10 / 12 page 10 Applications Information Power Consumption The HCPL-90xx and HCPL-09xx CMOS digital isolators achieves low power consumption from the manner by which they transmit data across isolation barrier. By detecting the edge transitions of the input logic signal and con- verting this to a narrow current pulse, which drives the isolation barrier, the isolator then latches the input logic state in the output latch. Since the current pulses are narrow, about 2.5 ns wide, the power consumption is indepen- dent of mark-to-space ratio and solely dependent on frequency. The approximate power supply current per channel is: I(Input) = 40(f/fmax)(1/4) mA where f = operating frequency, fmax = 50 MHz. Signal Status on Start-up and Shut Down To minimize power dissipation, the input signals to the channels of HCPL-90xx and HCPL-09xx digital isolators are differenti- ated and then latched on the output side of the isolation barrier to reconstruct the signal. This could result in an ambigu- ous output state depending on power up, shutdown and power loss sequencing. Therefore, the designer should consider the inclusion of an initialization signal in this start-up circuit. Bypassing and PC Board Layout The HCPL-90xx and HCPL-09xx digital isolators are extremely easy to use. No external interface circuitry is required because the isolators use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 1, the only external components required for proper operation are two 47 nF ceramic capacitors for decoupling the power supplies. For each capaci- tor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 2 illustrates the recommended printed circuit board layout for the HCPL-9000 or HCPL-0900. For data rates in excess of 10MBd, use of ground planes for both GND 1 and GND2 is highly recommended. Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900. 1 2 3 45 6 7 8 VDD1 IN1 C1 C2 Note: C1, C2 = 47 nF ceramic capacitors NC GND1 VDD2 OUT1 GND2 VOE Figure 2. Recommended Printed Circuit Board Layout. C2 VDD2 OUT1 GND2 VDD1 GND1 IN1 C1 VOE |
类似零件编号 - HCPL-0900 |
|
类似说明 - HCPL-0900 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |