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GS81302Q37AGD-333 数据表(PDF) 7 Page - GSI Technology |
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GS81302Q37AGD-333 数据表(HTML) 7 Page - GSI Technology |
7 / 24 page Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table A R Output Next State Q Q K (tn) K (tn) K (tn) K (tn+2) K (tn+2½) X 1 Deselect Hi-Z Hi-Z V 0 Read Q0 Q1 Notes: 1. X = Don’t Care, 1 = High, 0 = Low, V = Valid. 2. R is evaluated on the rising edge of K. 3. Q0 and Q1 are the first and second data output transfers in a read. Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table A W BWn BWn Input Next State D D K (tn + ½) K (tn) K (tn) K (tn + ½) K K (tn), (tn + ½) K (tn) K (tn + ½) V 0 0 0 Write Byte Dx0, Write Byte Dx1 D0 D1 V 0 0 1 Write Byte Dx0, Write Abort Byte Dx1 D0 X V 0 1 0 Write Abort Byte Dx0, Write Byte Dx1 X D1 X 0 1 1 Write Abort Byte Dx0, Write Abort Byte Dx1 X X X 1 X X Deselect X X Notes: 1. X = Don’t Care, H = High, L = Low, V = Valid. 2. W is evaluated on the rising edge of K. 3. D0 and D1 are the first and second data input transfers in a write. 4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.). Preliminary GS81302Q19/37AGD-450/400/375/333 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.00a 5/2017 7/24 © 2017, GSI Technology |
类似零件编号 - GS81302Q37AGD-333 |
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类似说明 - GS81302Q37AGD-333 |
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