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EP1K50 数据表(PDF) 12 Page - List of Unclassifed Manufacturers |
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EP1K50 数据表(HTML) 12 Page - List of Unclassifed Manufacturers |
12 / 86 page 12 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet EABs can be used to implement synchronous RAM, which is easier to use than asynchronous RAM. A circuit using asynchronous RAM must generate the RAM write enable signal, while ensuring that its data and address signals meet setup and hold time specifications relative to the write enable signal. In contrast, the EAB’s synchronous RAM generates its own write enable signal and is self-timed with respect to the input or write clock. A circuit using the EAB’s self-timed RAM must only meet the setup and hold time specifications of the global clock. When used as RAM, each EAB can be configured in any of the following sizes: 256 × 16; 512 × 8; 1,024 × 4; or 2,048 × 2. Figure 5 shows the ACEX 1K EAB memory configurations. Figure 5. ACEX 1K EAB Memory Configurations Larger blocks of RAM are created by combining multiple EABs. For example, two 256 × 16 RAM blocks can be combined to form a 256 × 32 block, and two 512 × 8 RAM blocks can be combined to form a 512 × 16 block. Figure 6 shows examples of multiple EAB combination. Figure 6. Examples of Combining ACEX 1K EABs 256 × 16 512 × 8 1,024 × 4 2,048 × 2 512 × 8 512 × 8 256 × 16 256 × 16 256 × 32 512 × 16 |
类似零件编号 - EP1K50 |
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类似说明 - EP1K50 |
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