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GS82583EQ18GK-400I 数据表(PDF) 9 Page - GSI Technology

部件名 GS82583EQ18GK-400I
功能描述  8Mb x 36 and 16Mb x 18 organizations available
Download  26 Pages
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制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS82583EQ18GK-400I 数据表(HTML) 9 Page - GSI Technology

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GS82583EQ18/36GK-500/450/400
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06 8/2017
9/26
© 2014, GSI Technology
Driver Impedance Control
Programmable Driver Impedance is implemented on the following output signals:
• CQ, CQ, Q, QVLD.
Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and VSS.
Driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.
Output Signal
Pull-Down Impedance (ROUTL)
Pull-Up Impedance (ROUTH)
CQ, CQ, Q, QVLD
RQ*0.2
 15%
RQ*0.2
 15%
Notes:
1. ROUTL and ROUTH apply when 175 RQ  225.
2. The mismatch between ROUTL and ROUTH is less than 10%, guaranteed by design.
ODT Impedance Control
Programmable ODT Impedance is implemented on the following input signals:
• CK, CK, KD, KD, SA, R, W, D.
ODT impedance is programmed by connecting an external resistor RT between the ZT pin and VSS.
ODT impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system
Input Signal
PZT[1:0]
MZT[1:0]
Pull-Down Impedance (RINL)
Pull-Up Impedance (RINH)
CK, CK, KD, KD
X0
XX
disabled
disabled
X1
01
RT
 15%
RT
 15%
10
RT*2
 20%
RT*2
 20%
SA, R, W
0X
XX
disabled
disabled
1X
01
RT
 15%
RT
 15%
10
RT*2
 20%
RT*2
 20%
D
XX
01
RT
 15%
RT
 15%
10
RT*2
 20%
RT*2
 20%
Notes:
1. When MZT[1:0] = 00, ODT is disabled on all inputs. MZT[1:0] = 11 is reserved for future use.
2. RINL and RINH apply when 105 RT  135
3. The mismatch between RINL and RINH is less than 10%, guaranteed by design.
4. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to VDDQ / 2 (i.e., to the switch point of the
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.
This could result in the device’s operating currents being higher.


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