SMP9210S datasheet(5/10 Pages) SUMMIT

部件名	SMP9210S

功能描述	Dual 10-bit Nonvolatile DAC

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制造商	SUMMIT [Summit Microelectronics, Inc.]

网页	http://www.summitmicro.com

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SMP9210 SMP9211 SMP9212

SUMMIT

MICROELECTRONICS, Inc.

type/address byte followed by the command byte.

They are will be enforced with or without a stop being

issued and the new register value is never stored in

the nonvolatile register.

Writing a value to a DAC can either be a write to the

DAC register only or a combined write to both the

DAC Register and its nonvolatile register. They are

identical with the one exception being the register

write does not entail issuing a stop condition;

whereas, the nonvolatile write operation is concluded

with a stop.

The sequence is to issue a start, followed by the

device type and bus address, with the read/write bit

set to zero. The SMP9210 will respond with an

acknowledge and the master will then issue the

command and follow-on data. In the example below

the write is to DAC1, where the command = 1001[b];

the dc bits are don't care, D9 and D8 are the MSBs of

the DAC value being written. The SMP9210 will then

respond with an acknowledge followed by the master

writing the last eight bits. In the first example shown,

no stop is generated after the SMP9210

acknowledge; therefore, the write is only to the

register. In the second example the SMP9210

acknowledge is followed by a stop; therefore, the

data is written to both the DAC register and to the

nonvolatile register.

Table 1. Command Structure.

MSB

LSB

7

6

5

4

3

2

1

0

Command

Function

1

0

1

dc

D9

D8

Write DAC1

Write 10-bit value to DAC1

1

0

1

0

dc

D9

D8

Write DAC2

Write 10-bit value to DAC2

1

0

1

dc

D9

D8

Write Both DACS

Write the same 10-bit value to DAC1

and DAC2

1

0

1

0

ZeroDAC1

Set DAC1 to Zero Scale (VREFL)

1

0

1

0

1

ZeroDAC2

Set DAC2 to Zero Scale (VREFL)

1

0

1

ZeroBOTH

Set DAC1 & DAC2 to Zero Scale (VREFL)

1

0

1

0

3FDAC1

Set DAC1 to Full Scale (VREFL)

1

0

1

0

1

3FDAC2

Set DAC2 to Full Scale (VREFL)

1

0

1

3FBOTH

Set DAC1 & DAC2 to Full Scale (VREFL)

1

dc

1

0

RecallDAC1

Recall E

2 to DAC1

1

dc

0

1

RecallDAC2

Recall E

2 to DAC2

1

dc

1

RecallBoth

Recall E

2 to Both DACs

1

0

dc

1

0

PDDAC1

Power Down DAC1 (VOUT to GND)

1

0

dc

0

1

PDDAC2

Power Down DAC2 (VOUT to GND)

1

0

dc

1

PDBOTH

Power Down Both DACs (VOUT to GND)

*dc = don't care

Writing to DACs Data Sequence (Volatile Write)

0

1

0

1

A

2

A

1

A

0

1

0

1

d

c

d

c

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

C

K

A

C

K

S

t

a

r

t

Device Type and Bus Address

W

Command

A

C

K

Writing to DACs Data Sequence (Nonvolatile Write)

0

1

0

1

A

2

A

1

A

0

1

0

1

d

c

d

c

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

S

t

a

r

t

A

C

K

A

C

K

A

C

K

S

t

o

p

Command Sequence (example command shown 3FDAC1)

0

1

0

1

A

2

A

1

A

0

1

0

1

0

S

t

a

r

t

Device Type and Bus Address

W

A

C

K

Command

A

C

K

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