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6PAIC3109TWRHMRQ1 数据表(PDF) 55 Page - Texas Instruments |
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6PAIC3109TWRHMRQ1 数据表(HTML) 55 Page - Texas Instruments |
55 / 111 page 55 TLV320AIC3109-Q1 www.ti.com SLASE93 – AUGUST 2017 Product Folder Links: TLV320AIC3109-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.6.2.19 Register 19: MIC1P/LINE1P to ADC Control Register (address = 13h) [reset = 0111 1000], Page 0 Figure 49. Register 19 7 6 5 4 3 2 1 0 MIC1P/LINE1P Single- Ended vs Fully Differential Control MIC1P/LINE1P Input Level Control for ADC PGA Mix ADC Channel Power Control ADC PGA Soft-Stepping Control R/W-0h R/W-1h R/W-0h R/W-0h Table 27. Register 19 Field Descriptions Bit Field Type Reset Description 7 MIC1P/LINE1P Single-Ended vs Fully Differential Control R/W 0h MIC1P/LINE1P single-ended vs fully differential control. 0: MIC1P/LINE1P is configured in single-ended mode 1: MIC1P/LINE1P and MIC1M/LINE1M are configured in fully differential mode 6:3 MIC1P/LINE1P Input Level Control for ADC PGA Mix R/W 1h MIC1P/LINE1P input level control for ADC PGA mix. Setting the input level control to one of the following gains automatically connects LINE1L to the ADC PGA mix. 0000: Input level control gain = 0 dB 0001: Input level control gain = –1.5 dB 0010: Input level control gain = –3 dB 0011: Input level control gain = –4.5 dB 0100: Input level control gain = –6 dB 0101: Input level control gain = –7.5 dB 0110: Input level control gain = –9 dB 0111: Input level control gain = –10.5 dB 1000: Input level control gain = –12 dB 1001–1110: Reserved; do not write these sequences to these register bits 1111: LINE1L is not connected to the ADC PGA 2 ADC Channel Power Control R/W 0h ADC channel power control. 0: ADC channel is powered down 1: ADC channel is powered up 1:0 ADC PGA Soft-Stepping Control R/W 0h ADC PGA soft-stepping control. 00: ADC PGA soft-stepping at one time per sample period 01: ADC PGA soft-stepping at one time per two sample periods 10–11: ADC PGA soft-stepping is disabled 7.6.2.20 Register 20: Reserved (address = 14h) [reset = 0111 1000], Page 0 Figure 50. Register 20 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 0 R-0h R-1h R-1h R-1h R-1h R-0h R-0h R-0h Table 28. Register 20 Field Descriptions Bit Field Type Reset Description 7:0 Reserved. R 0111 1000h Reserved. Always write 0111 1000 to these bits |
类似零件编号 - 6PAIC3109TWRHMRQ1 |
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类似说明 - 6PAIC3109TWRHMRQ1 |
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