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6PAIC3109TWRHMRQ1 数据表(PDF) 49 Page - Texas Instruments |
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6PAIC3109TWRHMRQ1 数据表(HTML) 49 Page - Texas Instruments |
49 / 111 page 49 TLV320AIC3109-Q1 www.ti.com SLASE93 – AUGUST 2017 Product Folder Links: TLV320AIC3109-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.6.2.8 Register 7: Codec Data-Path Setup Register (address = 7h) [reset = 0000 0000], Page 0 Figure 38. Register 7 7 6 5 4 3 2 1 0 fS(ref) Setting ADC Dual-Rate Control DAC Dual-Rate Control DAC Data Path Control 0 0 0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 16. Register 7 Field Descriptions Bit Field Type Reset Description 7 fS(ref) Setting R/W 0h This bit controls the fS(ref) setting. This register setting controls timers related to the AGC time constants. 0: fS(ref) = 48 kHz 1: fS(ref) = 44.1 kHz 6 ADC Dual-Rate Control R/W 0h 0: ADC dual-rate mode is disabled 1: ADC dual-rate mode is enabled The ADC dual-rate mode must match the DAC dual-rate mode. 5 DAC Dual-Rate Control R/W 0h 0: DAC dual-rate mode is disabled 1: DAC dual-rate mode is enabled 4:3 DAC Data Path Control R/W 0h 00: DAC data path is off (muted) 01: DAC data path plays left-channel input data 10: DAC data path plays right-channel input data 11: DAC data path plays mono mix of left- and right-channel input data 2:0 Reserved R/W 0h Reserved. Always write zeros to these bits. 7.6.2.9 Register 8: Audio Serial Data Interface Control Register A (address = 8h) [reset = 0000 0000], Page 0 Figure 39. Register 8 7 6 5 4 3 2 1 0 Bit Clock Directional Control Word Clock Directional Control Serial Output Data Driver Bit, Word Clock Drive Control 0 0 0 0 R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h Table 17. Register 8 Field Descriptions Bit Field Type Reset Description 7 Bit Clock Directional Control R/W 0h Bit clock directional control. 0: BCLK is an input (slave mode) 1: BCLK is an output (master mode) 6 Word Clock Directional Control R/W 0h Word clock directional control. 0: WCLK is an input (slave mode) 1: WCLK is an output (master mode) 5 Serial Output Data Driver R/W 0h Serial output data driver (DOUT) 3-state control. 0: Do not place DOUT in a high-impedance state when valid data are not being sent 1: Place DOUT in high-impedance state when valid data are not being sent 4 Bit, Word Clock Drive Control R/W 0h Bit, word clock drive control. 0: BCLK, WCLK do not continue to be transmitted when running in master mode if the codec is powered down 1: BCLK, WCLK continue to be transmitted when running in master mode, even if the codec is powered down 3 Reserved R 0h Reserved. Always write zeros to these bits. 2:0 Reserved R/W 0h Reserved. Always write zeros to these bits. |
类似零件编号 - 6PAIC3109TWRHMRQ1 |
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类似说明 - 6PAIC3109TWRHMRQ1 |
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