off, blocking current flow from the input, and then turns the

NFET synchronous rectifier on. The inductor draws current

from ground through the NFET to the output filter capacitor

and load, which ramps the inductor current down with a

slope of

The output filter stores charge when the inductor current is

high, and releases it when low, smoothing the voltage across

the load.

PWM OPERATION

During PWM operation the converter operates as a voltage-

mode controller with input voltage feed forward. This allows

the converter to achieve excellent load and line regulation.

The DC gain of the power stage is proportional to the input

voltage. To eliminate this dependence, feed forward in-

versely proportional to the input voltage is introduced.

Internal Synchronous Rectification

While in PWM mode, the LM3670 uses an internal NFET as

a synchronous rectifier to reduce rectifier forward voltage

drop and associated power loss. Synchronous rectification

provides a significant improvement in efficiency whenever

the output voltage is relatively low compared to the voltage

drop across an ordinary rectifier diode.

Current Limiting

A current limit feature allows the LM3670 to protect itself and

external components during overload conditions PWM mode

implements cycle-by-cycle current limiting using an internal

comparator that trips at 620 mA (typ).

PFM OPERATION

At very light loads, the converter enters PFM mode and

operates with reduced switching frequency and supply cur-

rent to maintain high efficiency.

The party will automatically transition into PFM mode when

either of two conditions occurs for a duration of 32 or more

clock cycles:

A. The inductor current becomes discontinuous

B. The peak PMOS switch current drops below the I

MODE

level:

During PFM operation, the converter positions the output

voltage slightly higher than the nominal output voltage during

PWM operation, allowing additional headroom for voltage

drop during a load transient from light to heavy load. The

PFM comparators sense the output voltage via the feedback

pin and control the switching of the output FETs such that the

output voltage ramps between 0.8% and 1.6% (typ) above

the nominal PWM output voltage. If the output voltage is

below the ‘high’ PFM comparator threshold, the PMOS

power switch is turned on. It remains on until the output

voltage exceeds the ‘high’ PFM threshold or the peak current

exceeds the I

in PFM mode is:

Once the PMOS power switch is turned off, the NMOS

power switch is turned on until the inductor current ramps to

zero. When the NMOS zero-current condition is detected,

the NMOS power switch is turned off. If the output voltage is

below the ‘high’ PFM comparator threshold (see Figure 5),

the PMOS switch is again turned on and the cycle is re-

peated until the output reaches the desired level. Once the

output reaches the ‘high’ PFM threshold, the NMOS switch is

turned on briefly to ramp the inductor current to zero and

then both output switches are turned off and the part enters

an extremely low power mode. Quiescent supply current

during this ‘sleep’ mode is less than 30 µA, which allows the

part to achieve high efficiencies under extremely light load

conditions. When the output drops below the ‘low’ PFM

threshold, the cycle repeats to restore the output voltage to

∼1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (see

Figure 5) causing the output voltage to fall below the ‘low2’

PFM threshold, the part will automatically transition into

fixed-frequency PWM mode.

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