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AM24LC21IN 数据表(PDF) 11 Page - List of Unclassifed Manufacturers

部件名 AM24LC21IN
功能描述  Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

AM24LC21IN 数据表(HTML) 11 Page - List of Unclassifed Manufacturers

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AM24LC21
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
(Preliminary)
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
11/13
S
T
O
P
N
O
A
C
K
S
S
T
A
R
T
Control
Byte
Word
address
Control
Byte
Bus activity
SDA Line
Bus activity
Master
A
C
K
A
C
K
A
C
K
Data(n)
P
S
S
T
A
R
T
Figure 7-2. Random read
S
T
O
P
N
O
A
C
K
Data(n)
Data(n+1)
Data(n+2)
Bus activity
SDA Line
Bus activity
Master
A
C
K
A
C
K
A
C
K
Data(n+X)
P
A
C
K
Contro
Byte
Figure 7-3. Sequential read
Pin Descriptions (Continued)
SDA
This pin is used to transfer addresses and data into
and out of the device, when the device is in the
bi-directional mode. In the transmit-only mode,
which only allows data to be read from the device,
data is also transferred on the SDA pin. This pin is
an open drain terminal, therefore the SDA bus
requires a pull-up resistor to VCC (typical 10k for
100 Khz, 1k for 400 Khz).
For normal data transfer in the bi-directional mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for
indicating the START and STOP conditions.
SCL
This pin is the clock input for the bi-directional
mode, and is used to synchronize data transfer to
and from the device. It is also used as the signaling
input to switch the device from the transmit only
mode to the bi-directional mode. It must remain
high for the chip to continue operation in the
transmit only mode.
VCLK
This pin is the clock input for the transmit only
mode. In the transmit only mode, each bit is
clocked out on the rising edge of this signal. In the
bi-directional mode, a high logic level is required on
this pin to enable write capability.
WP
When using the AM24LC21 in the bi-directional
Mode, the VCLK pin operates as the write protect
control pin. Setting VCLK high allows normal write
operations, while setting VCLK low prevents writing
to any location in the array. Connecting the VCLK
pin to VSS would allow the AM24LC21 to operate
as a serial ROM, although this configuration would
prevent using the device in the transmit-only mode.
If WP is connected to GND, PROGRAM operation
onto the whole memory will not be executed. READ
operation are possible. If WP is connected to Vcc,
normal
memory
operation
is
enabled,
READ/ WRITE over the entire memory is possible.


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