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MCM20027 数据表(PDF) 61 Page - Motorola, Inc

部件名 MCM20027
功能描述  Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor
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制造商  MOTOROLA [Motorola, Inc]
网页  http://www.freescale.com
标志 MOTOROLA - Motorola, Inc

MCM20027 数据表(HTML) 61 Page - Motorola, Inc

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© MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
61
ImageMOS
ImageMOS
The Pixel Data Stream Control Register allows the user to select how the output pixel data stream is encoded/for-
matted.
The vcb bit allows the user to force all the Blanking data coming out of the A2D to be 0.
The vcg bit allows the user to choose between encoded pixel data output stream or non-encoded pixel data output
stream.
The vcc bit allows the user to clip the output active pixel data to lie between 001 and 3FE
The default mode (Normal Mode) has the SOF, HCLK, VCLK etc. signals being utilised to indicate the start of data
and the end of data. (Figure 2, on page7 and Figure 14, on page 20)
Register Value = 00h
Another mode, Video Mode is a mode where the SOF and Row start/end signals are encoded (contained) in the
Active Pixel data stream. In addition, all data that is not a SOF, Row start/end, or Active pixel data are forced to 0.
i.e. all Blanking data from the A2D are forced to 0. The following sequence identifies the signals below: (see Figure
, on page 30)
a) SOF (1st Row of Pixel Data) - “3FF x 4)
b) Start of all other Rows - “3FF x 2” then “000 x 2”
2 - 0
HCLK
Delay
Delay = ((hckd[d]-4)x 0.5) - 16 MCLKs
100b
Address
64h
HCLK Control
Default
5Ch
msb (7)
6
5
4
3
2
1
lsb (0)
x
FUO
FUO
FUO
FUO
hckd[2]
hckd[1]
hckd[0]
Table 52. HCLK Delay Register


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