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AD9286BCPZRL7-500 数据表(PDF) 11 Page - Analog Devices

部件名 AD9286BCPZRL7-500
功能描述  8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9286BCPZRL7-500 数据表(HTML) 11 Page - Analog Devices

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AD9286
Data Sheet
Rev. C | Page 10 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
AVDD
AVDD
AUXCLK+
AUXCLK–
RBIAS
AUXCLKEN
DRGND
DRVDD
D0– (LSB)
D0+ (LSB)
D1–
D1+
AVDD
CLK+
CLK–
CSB
SDIO/PWDN
SCLK
OE
DRGND
DRVDD
D7+ (MSB)
D7– (MSB)
35
AVDD
36
34
33
32
31
30
29
28
27
26
25
AD9286
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG
GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT
DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
ADC Power Pins
1, 2, 35, 36, 37, 40, 42,
44, 45, 48
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
8, 27
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
7, 28
DRGND
Ground
Digital Output Ground.
0
AGND
Ground
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the
package. This is the only ground connection, and it must be soldered to
the PCB analog ground to ensure proper functionality and heat dissipation,
noise, and mechanical strength benefits.
ADC Analog Pins
39
VIN1+
Input
Differential Analog Input Pin (+) for Channel 1.
38
VIN1−
Input
Differential Analog Input Pin (−) for Channel 1.
46
VIN2+
Input
Differential Analog Input Pin (+) for Channel 2.
47
VIN2−
Input
Differential Analog Input Pin (−) for Channel 2.
43
VREF
Input/output
Voltage Reference Input/Output.
5
RBIAS
Input/output
External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND.
41
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
34
CLK+
Input
ADC Clock Input—True.
33
CLK−
Input
ADC Clock Input—Complement.
3
AUXCLK+
Input
Auxiliary ADC Clock Input—True.
4
AUXCLK−
Input
Auxiliary ADC Clock Input—Complement.
Digital Inputs
6
AUXCLKEN
Input
Auxiliary Clock Input Enable.
29
OE
Input
Digital Enable (Active Low) to Tristate Output Data Pins.
Digital Outputs
26
D7+ (MSB)
Output
Output Data 7—True.
25
D7− (MSB)
Output
Output Data 7—Complement.
24
D6+
Output
Output Data 6—True.
23
D6−
Output
Output Data 6—Complement.
22
D5+
Output
Output Data 5—True.
21
D5−
Output
Output Data 5—Complement.


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