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AD9286BCPZRL7-500 数据表(PDF) 7 Page - Analog Devices |
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AD9286BCPZRL7-500 数据表(HTML) 7 Page - Analog Devices |
7 / 28 page AD9286 Data Sheet Rev. C | Page 6 of 27 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 60 500 MHz CLK Period (tCLK) Full 2 Ns CLK Pulse Width High (tCH) Full 1 Ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 3.7 ns DCO Propagation Delay (tDCO) Full 3.7 ns DCO to Data Skew (tSKEW) Full −280 −60 100 ps Pipeline Delay (Latency) Full 11 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time1 Full 500 μs OUT-OF-RANGE RECOVERY TIME Full 4 Cycles 1 Wake-up time is dependent on the value of the decoupling capacitors. SPI TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns Timing Diagrams N – 1 N – 2 N + 1 M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 M – 7 N – 8 N + 2 N + 4 N + 3 N tCH tCLK M + 5 M + 4 M + 3 M + 1 M + 2 tA M M – 1 VIN1+, VIN1– VIN2+, VIN2– CLK+ CLK– DCO+, DCO– DATA tA tDCO tSKEW tPD Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default) |
类似零件编号 - AD9286BCPZRL7-500 |
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类似说明 - AD9286BCPZRL7-500 |
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