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ZL30100 数据表(PDF) 11 Page - Zarlink Semiconductor Inc

部件名 ZL30100
功能描述  T1/E1 System Synchronizer
Download  34 Pages
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制造商  ZARLINK [Zarlink Semiconductor Inc]
网页  http://www.zarlink.com
标志 ZARLINK - Zarlink Semiconductor Inc

ZL30100 数据表(HTML) 11 Page - Zarlink Semiconductor Inc

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ZL30100
Data Sheet
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Zarlink Semiconductor Inc.
Figure 3 - Reference Monitor Circuit
Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer requalify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure
4.
Figure 4 - Behaviour of the Dis/Requalify Timer
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the
REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the
mode (Holdover/Normal) of the DPLL.
Reference Frequency
Detector
Single Cycle
Monitor
Precise Frequency
Monitor
Coarse Frequency
Monitor
dis/requalify
timer
REF0 /
REF1
OR
OR
REF_DIS= reference disrupted.
This is an internal signal.
Mode select
state machine
HOLDOVER
REF_DIS
REF_FAIL0 /
REF_FAIL1
2.5 s
10 s
current REF
timer
REF_FAIL
SCM or CFM failure
HOLDOVER


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