NBSG16MMN datasheet(8/12 Pages) ONSEMI

部件名	NBSG16MMN

功能描述	2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

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制造商	ONSEMI [ON Semiconductor]

网页	http://www.onsemi.com

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NBSG16M

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Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V

−40

°C

25

°C

85

°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOUTPP

Output Voltage Amplitude

fin < 7 GHz

(See Figure 4) (Note 15)

fin < 10 GHz

300

200

400

250

300

200

400

250

300

100

400

150

mV

tPLH,

tPHL

Propagation Delay to

Output Differential

90

110

150

100

120

150

100

125

155

ps

tSKEW

Duty Cycle Skew (Note 16)

3

15

3

15

3

15

ps

tJITTER

RMS Random Clock Jitter (Note 18)

fin < 10 GHz

Peak−to−Peak Data Dependent Jitter (Note 19)

fin < 10 Gb/s

0.2

8

1

15

0.2

8

1

15

0.2

8

1.0

15

ps

VINPP

Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 17)

75

2500

75

2500

75

2500

mV

tr

tf

Output Rise/Fall Times @ 1 GHz

Q, Q

(20% − 80%)

21

35

53

21

35

53

21

35

53

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

15. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50

W to VCC. Input edge rates 40 ps (20% − 80%).

16. See Figure 5 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.

17. VINPP(max) cannot exceed VCC − VEE. (Applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single−ended measurement

operating in differential mode.

18. Additive RMS jitter with 50% duty cycle clock signal at 10GHz.

19. Additive Peak−to−Peak data dependent jitter with NRZ PRBS231−1 data rate at 10 Gb/s.

Figure 4. Output Voltage Amplitude (VOUTPP) versus

Input Clock Frequency (fin) at Ambient Temperature (Typical)

0

50

100

150

200

250

300

350

400

450

500

01

23456

7

8

9

10

FREQUENCY (GHz)

VCC − VEE = 3.3 V

VCC − VEE = 2.5 V

类似零件编号 - NBSG16MMN

制造商	部件名	数据表	功能描述
ON Semiconductor	NBSG16MMN	149Kb / 11P	2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2006 ??Rev. 5
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类似说明 - NBSG16MMN

制造商	部件名	数据表	功能描述
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NBSG16MMN 数据表(PDF) 8 Page - ON Semiconductor

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