CDCVF2505PWG4 datasheet(6/23 Pages) TI1

部件名	CDCVF2505PWG4

功能描述	3.3-V Clock Phase-Lock Loop Clock Driver

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制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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f − Frequency − MHz

45.0

47.5

50.0

52.5

55.0

25

50

75

100

125

150

175

200

G004

Load: CLKOUT = 12 pF || 500 W,

Yn = 25 pF || 500 W

f − Frequency − MHz

0

100

200

300

400

500

25

50

75

100

125

150

175

200

G005

Typical Values @ 3.3 V,

TA = 25°C

f − Frequency − MHz

−150

−100

−50

0

50

100

150

0

50

100

150

200

G003

Load: CLKOUT = 21 pF || 500 W,

Yn = 25 pF || 500 W

f − Frequency − MHz

0

100

200

300

400

500

25

50

75

100

125

150

175

200

G002

Load: CLKOUT = 12 pF || 500 W,

Yn = 25 pF || 500 W

6

CDCVF2505

SCAS640G – JULY 2000 – REVISED AUGUST 2016

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Product Folder Links: CDCVF2505

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(1)

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for

propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not

apply for input modulation under SSC application.

(2)

All typical values are at respective nominal VDD and 25°C

(3)

The tsk(o) specification is only valid for equal loading of all outputs.

7.7 Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V ±0.3 V

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP(2)

MAX

UNIT

tpd

Propagation delay, normalized

(see Figure 2)

CLKIN to Yn, f = 66 MHz to 200 MHz

–150

150

ps

tsk(o)

Output skew(3)

Yn to Yn

150

ps

tc(jit_cc)

Jitter (cycle-to-cycle)

(see Figure 4)

f = 66 MHz to 200 MHz

70

150

ps

f = 24 MHz to 50 MHz

200

400

odc

Output duty cycle

(see Figure 3)

f = 24 MHz to 200 MHz at 50% VDD

45%

55%

tr

Rise time

VO = 0.4 V to 2 V

0.5

2

ns

tf

Fall time

VO = 2 V to 0.4 V

0.5

2

ns

7.8 Typical Characteristics

at 3.3 V, 25°C (unless otherwise noted)

Figure 1. tpd, Propagation Delay Time vs Frequency

Figure 2. tpd, Typical Propagation Delay Time

vs Frequency (Tuned for Minimum Delay)

Figure 3. Duty Cycle vs Frequency

Figure 4. Cycle-Cycle Jitter vs Frequency

类似零件编号 - CDCVF2505PWG4

制造商	部件名	数据表	功能描述
Texas Instruments	CDCVF2505PW	369Kb / 14P	[Old version datasheet] 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
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	CDCVF2505PWR	549Kb / 14P	[Old version datasheet] 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
	CDCVF2505PWRG4	369Kb / 14P	[Old version datasheet] 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

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类似说明 - CDCVF2505PWG4

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