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TPD2S701-Q1 数据表(PDF) 8 Page - Texas Instruments |
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TPD2S701-Q1 数据表(HTML) 8 Page - Texas Instruments |
8 / 34 page 8 TPD2S701-Q1 SLLSEY0 – APRIL 2017 www.ti.com Product Folder Links: TPD2S701-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Power Supply and Supply Current Consumption Chracteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ID_OFF_LEAK_S TB Mode 0. Measured flowing into D+ or D– supply, VPWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V –1 1 µA ID_ON_LEAK_ST B Mode 0. Measured flowing into D+ or D– supply, VPWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V –1 1 µA IVD_OFF_LEAK_ STB Mode 0. Measured flowing out of VD+ or VD– supply, VPWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V 120 IVD_ON_LEAK_S TB Mode 0. Measured flowing out of VD+ or VD– supply, VPWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V 120 µA IVPWR_TO_VRE F_LEAK Leakage from VPWR to VREF Use standard mode 0. Set VREF = 0 V. Measured current flowing out of VREF pin 1 µA IVREF_TO_VPW R_LEAK Leakage from VREF to VPWR Use standard mode 0. Set VPWR = 0 V. Measured as current flowing out of VPWR pin 1 µA 6.9 Timing Requirements over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT ENABLE PIN AND VREF FAST CHARGE TVREF_CHG VREF fast charge time Time between when 5 V is applied to VPWR, and VREF reaches VVREF_FAST_CHG. Needs to happen before or at same time tON_STARTUP completes 0.5 1 ms TON_STARTU P_MODE0 Device turnon time from UVLO mode 0 Mode 0. EN = 0 V, measured from VPWR and VREF = UVLO+ to data FET ON, VPWR comes to UVLO + second. Place 3.3 V on VD±. Ramp VREF to 3.3 V, then VPWR to 5 V and measure the time it takes for D± to reach 90% of VD± 0.5 1 ms TON_STARTU P_MODE1 Device turnon time from UVLO mode 1 Informative. mode 1. EN = 0 V, measured from VPWR = UVLO+ to data FET ON 0.5 + TCHG_C VREF ms TON_STARTU P_MODE1_3.3V Device turnon time from UVLO mode 1 Mode 1. EN = 0 V, measured from VPWR = UVLO + to data FET ON, CVREF = 1 µF, VREF_FINAL = 3.3 V. Measure the time it takes for D± to reach 90% of VD± 0.6 1 ms TON_EN_MOD E0 Device turnon time mode 0 Mode 0. VPWR = 5 V, VREF = 3.3 V, time from EN is asserted until data FET is ON. Place 3.3 V on VD±, measure the time it takes for D± to reach 90% of VD± 150 µs TON_EN_MOD E1 Device turnon time mode 1 Mode 1. VPWR = 5 V, VREF_INITIAL = 0 V, time from EN is asserted until data FET is ON. Place 3.3 V on VD±, measure the time it takes for D± to reach 90% of VD± 150 + TCHG_V REF µs TON_EN_MOD E1_3.3V Device turnon time mode 1 for VREF = 3.3 V Mode 1. VPWR = 5 V, VREF_INITIAL = 0 V, time from EN is asserted until data FET is ON. Place 3.3 V on VD±, measure the time it takes for D± to reach 90% of VD±. CVREF = 1 µF, VREF_FINAL = 3.3 V 300 µs TOFF_EN Device turnoff time Mode 0 or 1. VPWR = 5 V, VREF = 3.3 V, time from EN is deasserted until data FET is off. Place 3.3 V on VD±, measure the time it takes for D± to fall to 10% of VD±, RD± = 45 Ω 5 µs TCHG_CVREF Time to charge CVREF Informative. Mode 1. Time from VREF = 0 V to 80% × VREF_FINAL after EN transitions from high to low (CVREF × 0.8 (VREF_FI NAL)/(IC HG_VREF ) s TCHG_CVREF _3.3V Time to charge CVREF to 3.3 V Mode 1. Time from VREF = 0 V to 90% × 3.3 V after EN transitions from high to low, CVREF = 1 µF 132 µs |
类似零件编号 - TPD2S701-Q1 |
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类似说明 - TPD2S701-Q1 |
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