3

AT94S Secure Family

2314D–FPSLI–2/04

Figure 1. AT94S Architecture

The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe-

cuting powerful instructions in a single-clock-cycle, and allows system designers to

optimize power consumption versus processing speed. The AVR core is based on an

enhanced RISC architecture that combines a rich instruction set with 32 general-pur-

pose working registers. All 32 registers are directly connected to the Arithmetic Logic

Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code-efficient while

achieving throughputs up to ten times faster than conventional CISC microcontrollers at

the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA

configuration SRAM and AVR instruction code SRAM are automatically loaded at sys-

tem power-up using Atmel’s in-system programmable AT17 Series EEPROM

configuration memories, which are part of the AT94S Multi-chip Module (MCM).

tion with the FPSLIC architecture to help reduce overall time-to-market by integrating

microcontroller development and debugging, FPGA development, place and route, and

complete system co-verification in one easy-to-use software tool.

5 - 40K Gates FPGA

Up to

16K x 8

Data

SRAM

Up to 16K x 16

Program

SRAM Memory

PROGRAMMABLE I/O

with

Multiply

Two 8-bit

Timer/Counters

16 Prog. I/O

Lines

I/O

I/O

I/O

2-wire Serial

Unit

Up to 16

Decoded

Address Lines

4 Interrupt Lines

Configuration Logic

Configuration

EEPROM

I/O

For ISP

and Chip

Erase

Two Serial

UARTs