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TNETV2501INPGF 数据表(PDF) 87 Page - Texas Instruments |
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TNETV2501INPGF 数据表(HTML) 87 Page - Texas Instruments |
87 / 197 page Functional Overview 87 December 2002 − Revised November 2008 SPRS206K 3.10.7.2 IDLE Status Register (ISTR) 15 9 8 Reserved IPORTIS R, 0000000 R, 0 76 54 32 10 MPORTIS XPORTIS EMIFIS CLKIS PERIS ICACHEIS MPIS CPUIS R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3−27. IDLE Status Register Layout (0x0002) Table 3−28. IDLE Status Register Bit Field Description BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15−9 R 0000000 Reserved IPORTIS 8 R 0 IPORT idle status bit. The IPORT is used for all ICACHE transactions. IPORTIS = 0: IPORT is active IPORTIS = 1: IPORT is disabled MPORTIS 7 R 0 MPORT idle status bit. The MPORT is used for all DMA and HPI transactions. MPORTIS = 0: MPORT is active MPORTIS = 1: MPORT is disabled XPORTIS 6 R 0 XPORT idle status bit. The XPORT is used for all I/O memory transactions. XPORTIS = 0: XPORT is active XPORTIS = 1: XPORT is disabled EMIFIS 5 R 0 External Memory Interface (EMIF) idle status bit EMIFIS = 0: EMIF module is active EMIFIS = 1: EMIF module is disabled CLKIS 4 R 0 Device clock generator idle status bit CLKIS = 0: Device clock generator module is active CLKIS = 1: Device clock generator is disabled PERIS 3 R 0 Peripheral idle status bit PERIS = 0: All peripheral modules are active PERIS = 1: All peripheral modules are disabled ICACHEIS 2 R 0 ICACHE idle status bit ICACHEIS = 0: ICACHE module is active ICACHEIS = 1: ICACHE module is disabled MPIS 1 R 0 DMA and HPI idle status bit MPIS = 0: DMA and HPI modules are active MPIS = 1: DMA and HPI modules are disabled CPUIS 0 R 0 CPU idle status bit CPUIS = 0: CPU module is active CPUIS = 1: CPU module is disabled |
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