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TNETV2501INPGF 数据表(PDF) 37 Page - Texas Instruments |
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TNETV2501INPGF 数据表(HTML) 37 Page - Texas Instruments |
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37 / 197 page  Introduction 37 December 2002 − Revised November 2008 SPRS206K Table 2−4. Signal Descriptions (Continued) Pin Name Function Other‡ Pin Type† Multiplexed Signal Name Test Pins (Continued) EMU0 I/O/Z J Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O by way of the IEEE standard 1149.1 scan system. The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not connected. Internal pullups have been included for this purpose. If the user chooses to disable these pins through the XBCR, external pullup resistors must be added to these two pins. EMU1/OFF I/O/Z J Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as I/O by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = low, EMU0 = high, EMU1/OFF = low The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not connected. Internal pullups have been included for this purpose. If the user chooses to disable these pins through the XBCR, external pullup resistors must be added to these two pins. † I = Input, O = Output, S = Supply, Z = High impedance ‡ Other Pin Characteristics: A − Internal pullup [always enabled] B − Internal pulldown [always enabled] C − Hysteresis input D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode. F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0). G − Pin can be configured as a general-purpose input. H − PIn can be configured as a general-purpose output. J − Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default]. L − Fail-safe pin M − Pin is in high-impedance during reset (RESET pin is low) |
类似零件编号 - TNETV2501INPGF |
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类似说明 - TNETV2501INPGF |
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