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TNETV1644ZDU6 数据表(PDF) 76 Page - Texas Instruments |
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TNETV1644ZDU6 数据表(HTML) 76 Page - Texas Instruments |
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76 / 306 page  TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 3-2. VDD3P3V_PWDN Register Descriptions (continued) BIT NAME DESCRIPTION EMIFA/VPSS Sub-Block 1 I/O Power Down Control. Controls the power of the 29 I/O pins in the EMIFA/VPSS Sub-Block 1. 2 EMBK1 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA/VPSS Sub-Block 0 I/O Power Down Control. Controls the power of the 21 I/O pins in the EMIFA/VPSS Sub-Block 0. 1 EMBK0 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). CLKOUT Block I/O Power Down Control. Controls the power of the 1 I/O pin in the CLKOUT Block. 0 CLKOUT 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). Device Configurations 76 Submit Documentation Feedback |
类似零件编号 - TNETV1644ZDU6 |
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类似说明 - TNETV1644ZDU6 |
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