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DRV8320RHRHAT 数据表(PDF) 35 Page - Texas Instruments |
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DRV8320RHRHAT 数据表(HTML) 35 Page - Texas Instruments |
35 / 89 page VGHx VINHx VINLx IGHx IDRIVE IHOLD VGLx ISTRONG tDRIVE tDEAD ISTRONG IGLx IDRIVE IHOLD tDEAD tDRIVE IDRIVE ISTRONG tDRIVE tDEAD tDEAD tDRIVE IHOLD IHOLD IHOLD IHOLD IHOLD ISTRONG IHOLD IDRIVE IHOLD IHOLD 35 DRV8320, DRV8320R DRV8323, DRV8323R www.ti.com SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017 Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state machine enables a strong pulldown ISTRONG current on the opposite MOSFET gate whenever a MOSFET is switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly. The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a command to change the state of the half-bridge it begins to monitor the gate voltage of the external MOSFET. If at the end of the tDRIVE period the VGS voltage has not reached the proper threshold the gate driver will report a fault. To ensure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will terminate if another PWM command is received while active. Additional details on the TDRIVE settings are described in the Register Maps section for SPI devices and in the Pin Diagrams section for hardware interface devices. Figure 27 shows an example of the TDRIVE state machine in operation. Figure 27. TDRIVE State Machine 8.3.1.4.3 Propagation Delay The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output change. This time comprises three parts consisting of the digital input deglitcher delay, the digital propagation delay, and the delay through the analog gate drivers. The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall propagation delay of the device. 8.3.1.4.4 MOSFET VDS Monitors The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the device VDS fault mode. |
类似零件编号 - DRV8320RHRHAT |
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类似说明 - DRV8320RHRHAT |
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