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DRV8320R 数据表(PDF) 5 Page - Texas Instruments

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部件名 DRV8320R
功能描述  6 to 60-V Three-Phase Smart Gate Driver
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

DRV8320R 数据表(HTML) 5 Page - Texas Instruments

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5
DRV8320, DRV8320R
DRV8323, DRV8323R
www.ti.com
SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
(1)
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
Pin Functions—40-Pin DRV8320R Devices
PIN
TYPE
(1)
DESCRIPTION
NAME
NO.
DRV8320RH
DRV8320RS
AGND
26
26
PWR
Device analog ground. Connect to system ground.
BGND
34
34
PWR
Buck regulator ground. Connect to system ground.
CB
35
35
PWR
Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins.
CPH
3
3
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL
2
2
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DVDD
27
27
PWR
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins.
This regulator can source up to 30 mA externally.
ENABLE
25
25
I
Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
FB
40
40
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GHA
7
7
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
14
14
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
15
15
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
9
9
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
12
12
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
17
17
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND
19
19
PWR
Device ground. Connect to system ground.
IDRIVE
22
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
28
28
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
30
30
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
32
32
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA
29
29
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB
31
31
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC
33
33
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE
21
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC
24
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
37
37
NC
No internal connection. This pin can be left floating or connected to system ground.
nFAULT
20
20
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS
24
I
Serial chip select. A logic low on this pin enables serial interface communication.
nSHDN
39
39
I
Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull below 1.25 V to
disable. Float to enable. Establish input undervoltage lockout with two resistor divider.
PGND
1
1
PWR
Device power ground. Connect to system ground.
SCLK
23
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI
22
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
21
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA
8
8
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
13
13
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
16
16
I
High-side source sense input. Connect to the high-side power MOSFET source.
SLA
10
10
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLB
11
11
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
18
18
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SW
36
36
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCP
4
4
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN
6
6
I
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS
23
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VIN
38
38
PWR
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VM
5
5
PWR
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.


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