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STP16CPP05XTTR 数据表(PDF) 11 Page - STMicroelectronics |
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STP16CPP05XTTR 数据表(HTML) 11 Page - STMicroelectronics |
11 / 31 page STP16CPP05 Timing diagrams DocID15379 Rev 5 11/31 5 Timing diagrams Table 9: Truth table CLOCK LE OE SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO _|¯ H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 _|¯ L L Dn + 1 No change Dn - 14 _|¯ H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X H Dn + 3 OFF Dn - 13 OUTn = ON when Dn = H OUTn = OFF when Dn = L. Figure 7: Timing diagram The latches circuit holds data when the LE terminal is Low. 1 When LE terminal is at high level, latch circuit does not hold the data it passes from the input to the output. 2 When OE terminal is at low level, output terminals OUT0 to OUT15 respond to the data, either ON or OFF. 3 When OE terminal is at high level, it switches off all the data on the output terminal. |
类似零件编号 - STP16CPP05XTTR |
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类似说明 - STP16CPP05XTTR |
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