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DDC232CGXGR Datasheet(数据表) 22 Page - Texas Instruments

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部件型号  DDC232CGXGR
说明  32-Channel, Current-Input Analog-to-Digital Converter
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DDC232CGXGR Datasheet(HTML) 22 Page - Texas Instruments

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t
INT
* tCMDR ) tSDCV
(20
32)t
DCLK
1000ms * 286.8ms
(640)(100ns)
+ 11.14 ³ 11 DDC232
Side B
Data
Side A
Data
t
INT
t
INT
t
CMDR
t
SDCV
CONV
DVALID
DCLK
DOUT
DDC232
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
www.ti.com
RETRIEVAL BEFORE CONV TOGGLES
(CONTINUOUS MODE)
(1)
Data retrieval before CONV toggles is the most
NOTE: (16 × 32)tDCLK is used for Format = 0, where
straightforward method. Data retrieval begins soon
tDCLK is the period of the data clock. For example, if
after DVALID goes low and finishes before CONV
tINT = 1000ms and DCLK = 10MHz, the maximum
toggles,
as
shown
in
Figure
20.
For
best
number of DDC232s with Format = 1 is shown in
performance, data retrieval must stop tSDCV before
Equation 2:
CONV toggles. This method is most appropriate for
longer integration times. The maximum time available
for readback is tINT – tCMDR – tSDCV.
(2)
For DCLK = 10MHz and CLK = 5MHz, the maximum
(or 13 for Format = 0)
number of DDC232s that can be daisy-chained
together (Format = 1) is calculated by Equation 1:
Figure 20. Readback Before CONV Toggles
Table 15. Timing Characteristics for Readback
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tSDCV
Data Retrieval Shutdown Before or After Edge of CONV
10
ms
22
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DDC232




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