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ADC10838CIN 数据表(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 ADC10838CIN
功能描述  10-Bit Plus Sign Serial I/O A/D Converters with MUX, Sample/Hold and Reference
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

ADC10838CIN 数据表(HTML) 6 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
The following specifications apply for Va e AVa e DVa ea50 VDC VREFa ea4096 VDC VREFb e VIN e GND
Vb eb50 VDC and fCLK e 25 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX
all other limits TA e TJ ea25 C (Note 16)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 11)
(Note 12)
(Limits)
AC CHARACTERISTICS
fCLK
Clock Frequency
30
25
MHz(max)
5
kHz(min)
Clock Duty Cycle
40
%(min)
60
%(max)
tC
Conversion Time
12
12
Clock
Cycles
5
5
m
s(max)
tA
Acquisition Time
45
45
Clock
Cycles
2
2
m
s(max)
tSCS
CS Set-Up Time Set-Up Time from Falling Edge of
14
30
ns(min)
CS to Rising Edge of Clock
(1 tCLK
(1 tCLK
(max)
b
14 ns)
b
30 ns)
tSDI
DI Set-Up Time Set-Up Time from Data Valid on
16
25
ns(min)
DI to Rising Edge of Clock
tHDI
DI Hold Time Hold Time of DI Data from Rising
2
25
ns(min)
Edge of Clock to Data not Valid on DI
tAT
DO Access Time from Rising Edge of CLK When
30
50
ns(min)
CS is ‘‘Low’’ during a Conversion
tAC
DO or SARS Access Time from CS Delay from
30
70
ns(max)
Falling Edge of CS to Data Valid on DO or SARS
tDSARS
Delay from Rising Edge of Clock to Falling Edge of
100
200
ns(max)
SARS when CS is ‘‘Low’’
tHDO
DO Hold Time Hold Time of Data on DO after
20
45
ns(max)
Falling Edge of Clock
tAD
DO Access Time from Clock Delay from Falling
40
80
ns(max)
Edge of Clock to Valid Data of DO
t1H t0H
Delay from Rising Edge of CS to DO or SARS
40
50
ns(max)
TRI-STATE
tDCS
Delay from Falling Edge of Clock to Falling Edge of
20
30
ns(min)
CS
tCS(H)
CS ‘‘HIGH’’ Time for AD Reset after Reading of
1 CLK
1 CLK
cycle(min)
Conversion Result
tCS(L)
ADC10731 Minimum CS ‘‘Low’’ Time to Start a
1 CLK
1 CLK
cycle(min)
Conversion
tSC
Time from End of Conversion to CS Going ‘‘Low’’
5 CLK
5 CLK
cycle(min)
tPD
Delay from Power-Down command to 10% of
1
m
s
Operating Current
tPC
Delay from Power-Up Command to Ready to Start
10
m
s
a New Conversion
CIN
Capacitance of Logic Inputs
7
pF
COUT
Capacitance of Logic Outputs
12
pF
6


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